phoebewang wrote:
Thanks @KanRobert !
https://github.com/llvm/llvm-project/pull/77733
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/77733
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phoebewang wrote:
> > > Why not return `i32` for 64-bit mask in 32-bit mode?
> >
> >
> > You mean in two `i32` registers? The problem is the inline asm constraint
> > has 1:1 map with physical register except corner cases. And represent a `k`
> > constraint into two GPR registers is inefficie
KanRobert wrote:
> > Why not return `i32` for 64-bit mask in 32-bit mode?
>
> You mean in two `i32` registers? The problem is the inline asm constraint has
> 1:1 map with physical register except corner cases. And represent a `k`
> constraint into two GPR registers is inefficient.
Is it repre
KanRobert wrote:
Why not return `i32` for 64-bit mask in 32-bit mode?
https://github.com/llvm/llvm-project/pull/77733
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https://github.com/RKSimon commented:
Should we add test coverage for the gpr <-> mask transfers?
https://github.com/llvm/llvm-project/pull/77733
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https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/77733
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