djtodoro wrote:
I will postpone this PR until I prepare big endian support, thank you all for
the comments!
https://github.com/llvm/llvm-project/pull/134065
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https://github.com/djtodoro closed
https://github.com/llvm/llvm-project/pull/134065
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@@ -337,13 +337,17 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList
&Args,
// - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
// - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
if (Triple.isRISCV32()) {
-if (Triple.getOS
@@ -1874,15 +1894,26 @@ static void findRISCVMultilibs(const Driver &D,
MultilibBuilder("lib64/lp64f").flag("-m64").flag("-mabi=lp64f");
MultilibBuilder Lp64d =
MultilibBuilder("lib64/lp64d").flag("-m64").flag("-mabi=lp64d");
+
+ SmallVector Endian;
+ if (Target
https://github.com/ilovepi approved this pull request.
LGTM. Probably give @mshockwave a chance to weigh in before landing, though.
https://github.com/llvm/llvm-project/pull/134065
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djtodoro wrote:
> There's a lot going on here that has absolutely no explanation (no comments
> in the code, and the commit message is a single sentence that tells me
> nothing of use), and it's doing multiple different things. There's changing
> default arch strings, which makes some sense (w
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/5] [clang][RISCV] Set default CPU for vendor
---
clang/
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/4] [clang][RISCV] Set default CPU for vendor
---
clang/
@@ -115,6 +115,20 @@
// MCPU-MIPS-P8700-SAME: "-target-feature" "+zba"
// MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb"
+// RUN: %clang --target=riscv64-mti-linux-gnu -### -c %s 2>&1| FileCheck
-check-prefix=MCPU-MTI-P8700 %s
djtodoro wrote:
Sure.
https://
topperc wrote:
No tests?
https://github.com/llvm/llvm-project/pull/134065
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https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor
---
clang/
@@ -424,8 +432,19 @@ std::string Linux::computeSysRoot() const {
const StringRef InstallDir = GCCInstallation.getInstallPath();
const StringRef TripleStr = GCCInstallation.getTriple().str();
const Multilib &Multilib = GCCInstallation.getMultilib();
+ std::string Path;
+
djtodoro wrote:
> No tests?
@topperc Added.
https://github.com/llvm/llvm-project/pull/134065
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https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/3] [clang][RISCV] Set default CPU for vendor
---
clang/
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp --
clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/lib/
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor
---
clang/
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor
---
clang/
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Djordje Todorovic (djtodoro)
Changes
Add support for MipsTechnologies for RISC-V targets.
---
Full diff: https://github.com/llvm/llvm-project/pull/134065.diff
6 Files Affected:
- (modified) clang/lib/Driver/ToolChains/Arch/RISCV.
https://github.com/djtodoro created
https://github.com/llvm/llvm-project/pull/134065
Add support for MipsTechnologies for RISC-V targets.
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/2] [
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