[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

https://github.com/lenary closed https://github.com/llvm/llvm-project/pull/128815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -974,17 +974,20 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, emitCFIForCSI(MBB, MBBI, getUnmanagedCSI(MF, CSI)); // Generate new FP. - if (hasFP(MF) && RVFI->getPushPopKind(MF) != - RISCVMachineFunctionInfo::PushPopKind::VendorXqc

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/128815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -974,17 +974,20 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, emitCFIForCSI(MBB, MBBI, getUnmanagedCSI(MF, CSI)); // Generate new FP. - if (hasFP(MF) && RVFI->getPushPopKind(MF) != - RISCVMachineFunctionInfo::PushPopKind::VendorXqc

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

lenary wrote: @topperc the two useful changes since you last reviewed are: - Adding a Release Note - Changing the conditions around frame pointers to ensure we don't emit a `add s0, sp, -` (as before), but that we do emit the `.cfi_def_cfa s0, 0` which informs dwarf/cfi that the way to calculat

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff 6e7f04266c5f729cf4bc5546e2bf29aad3e695f1 ee917b49d67aac155334e8c8ef33173788e6f649 --e

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/128815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -783,6 +783,54 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, } } +static bool isPush(unsigned Opcode) { + switch (Opcode) { + case RISCV::CM_PUSH: + case RISCV::QC_CM_PUSH: + case RISCV::QC_CM_PUSHFP: +return true; + default: +return fals

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -783,6 +783,54 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, } } +static bool isPush(unsigned Opcode) { + switch (Opcode) { + case RISCV::CM_PUSH: + case RISCV::QC_CM_PUSH: + case RISCV::QC_CM_PUSHFP: +return true; + default: +return fals

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -141,9 +141,38 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo { // We cannot use fixed locations for the callee saved spill slots if the // function uses a varargs save area. // TODO: Use a separate placement for vararg registers to enable Zcmp.

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -120,12 +144,7 @@ bool RISCVPushPopOpt::runOnMachineFunction(MachineFunction &Fn) { // If Zcmp extension is not supported, abort. const RISCVSubtarget *Subtarget = &Fn.getSubtarget(); - if (!Subtarget->hasStdExtZcmp()) -return false; - - // If frame pointer elimi

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -120,12 +144,7 @@ bool RISCVPushPopOpt::runOnMachineFunction(MachineFunction &Fn) { // If Zcmp extension is not supported, abort. const RISCVSubtarget *Subtarget = &Fn.getSubtarget(); - if (!Subtarget->hasStdExtZcmp()) -return false; - - // If frame pointer elimi

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -783,6 +783,54 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, } } +static bool isPush(unsigned Opcode) { + switch (Opcode) { + case RISCV::CM_PUSH: + case RISCV::QC_CM_PUSH: + case RISCV::QC_CM_PUSHFP: +return true; + default: +return fals

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -783,6 +783,54 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, } } +static bool isPush(unsigned Opcode) { + switch (Opcode) { + case RISCV::CM_PUSH: + case RISCV::QC_CM_PUSH: + case RISCV::QC_CM_PUSHFP: +return true; + default: +return fals

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

@@ -141,9 +141,38 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo { // We cannot use fixed locations for the callee saved spill slots if the // function uses a varargs save area. // TODO: Use a separate placement for vararg registers to enable Zcmp.

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-clang Author: Sam Elliott (lenary) Changes This adds support for Xqccmp to the following passes: - Prolog Epilog Insertion - reusing much of the existing push/pop logic, but extending it to cope with frame pointers an

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

llvmbot wrote: @llvm/pr-subscribers-clang-driver Author: Sam Elliott (lenary) Changes This adds support for Xqccmp to the following passes: - Prolog Epilog Insertion - reusing much of the existing push/pop logic, but extending it to cope with frame pointers and reorder the CFI information

[clang] [llvm] [RISCV] Xqccmp Code Generation (PR #128815)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Sam Elliott (lenary) Changes This adds support for Xqccmp to the following passes: - Prolog Epilog Insertion - reusing much of the existing push/pop logic, but extending it to cope with frame pointers and reorder the CFI information correctl