https://github.com/topperc closed
https://github.com/llvm/llvm-project/pull/75760
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/75760
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@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280",
SiFive7Model,
[TuneSiFive7,
TuneDLenFactor2]>;
+def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel,
+
@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280",
SiFive7Model,
[TuneSiFive7,
TuneDLenFactor2]>;
+def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel,
+
@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
-check-pref
@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
-check-pref
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-clang
Author: Craig Topper (topperc)
Changes
This is an out of order core with no vector unit. More information:
https://www.sifive.com/cores/performance-p450-470
Scheduler model and other tuning will come in separat
https://github.com/topperc created
https://github.com/llvm/llvm-project/pull/75760
This is an out of order core with no vector unit. More information:
https://www.sifive.com/cores/performance-p450-470
Scheduler model and other tuning will come in separate patches.
>From 22fd20164e9d061a451555
