[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

topperc wrote: > > The ISA is specified in this document too > > https://www.sifive.com/document-file/eic7700x-datasheet available here > > https://www.sifive.com/boards/hifive-premier-p550 > > None of the documentation is consistant nor complete reguarding the ISA: > > * [Product > Brief](h

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

camel-cdr wrote: > The ISA is specified in this document too > https://www.sifive.com/document-file/eic7700x-datasheet available here > https://www.sifive.com/boards/hifive-premier-p550 None of the documentation is consistant nor complete reguarding the ISA: * [Product Brief](https://www.sif

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

topperc wrote: > > > > I thought the P550 was supposed to support RV64GCB, but that would > > > > require Zbs support, which isn't listed here. > > > > > > > > > The P550 version in the HiFive Premier board does not support Zbs. ISA > > > string from /proc/cpuinfo is `rv64imafdch_zicsr_zifenc

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

wangpc-pp wrote: > > I thought the P550 was supposed to support RV64GCB, but that would require > > Zbs support, which isn't listed here. > > The P550 version in the HiFive Premier board does not support Zbs. ISA string > from /proc/cpuinfo is `rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf` Tha

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

topperc wrote: > I thought the P550 was supposed to support RV64GCB, but that would require > Zbs support, which isn't listed here. The P550 version in the HiFive Premier board does not support Zbs. ISA string from /proc/cpuinfo is `rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf` https://github.

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

camel-cdr wrote: I thought the P550 was supposed to support RV64GCB, but that wouls require Zbs support, which isn't listed here. https://github.com/llvm/llvm-project/pull/122164 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.ll

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/122164 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/122164 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/122164 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

llvmbot wrote: @llvm/pr-subscribers-clang-driver Author: Craig Topper (topperc) Changes This is the CPU in SiFive's HiFive Premier P550 development board. Scheduler model will come in a later patch. --- Full diff: https://github.com/llvm/llvm-project/pull/122164.diff 4 Files Affected:

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/122164 This is the CPU in SiFive's HiFive Premier P550 development board. Scheduler model will come in a later patch. >From 207face06fbb98c811aefd4d541e62d88f13f4bd Mon Sep 17 00:00:00 2001 From: Craig Topper Date: W