https://github.com/john-brawn-arm closed
https://github.com/llvm/llvm-project/pull/96903
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https://github.com/lenary approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/96903
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john-brawn-arm wrote:
> Thanks, LGTM.
>
> As a follow-up, can you check that the instructions generated from this
> builtin do inhibit the machine outliner? Maybe all GCS-modifying functions
> have to inhibit the machine outliner, I'm not 100% sure.
The GCS instructions don't inhibit the mach
john-brawn-arm wrote:
I've added a new change to work around a problem in intrinsic handling that's
detailed in
https://discourse.llvm.org/t/intrinsic-with-sideeffect-is-optimized-out/66053
(I previously had this workaround in, but removed it because it looked like it
was no longer needed, bu
https://github.com/john-brawn-arm updated
https://github.com/llvm/llvm-project/pull/96903
>From 123ebe17131fcfc7662be6759327b311e90fb16d Mon Sep 17 00:00:00 2001
From: John Brawn
Date: Tue, 25 Jun 2024 15:35:18 +0100
Subject: [PATCH 1/3] [AArch64] Implement GCS ACLE intrinsics
This adds intrin
https://github.com/lenary approved this pull request.
Thanks, LGTM.
As a follow-up, can you check that the instructions generated from this builtin
do inhibit the machine outliner? Maybe all GCS-modifying functions have to
inhibit the machine outliner, I'm not 100% sure.
https://github.com/ll
@@ -855,6 +863,25 @@ __rndrrs(uint64_t *__p) {
}
#endif
+/* 11.2 Guarded Control Stack intrinsics */
+#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
+static __inline__ void * __attribute__((__always_inline__, __nodebug__))
+__gcspr() {
+ return (void *)__builtin_arm_rsr6
https://github.com/hstk30-hw approved this pull request.
LGTM, don't known why the CI failed :>
https://github.com/llvm/llvm-project/pull/96903
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hstk30-hw wrote:
LGTM, don't know why the CI failed :>
https://github.com/llvm/llvm-project/pull/96903
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@@ -855,6 +863,25 @@ __rndrrs(uint64_t *__p) {
}
#endif
+/* 11.2 Guarded Control Stack intrinsics */
+#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
+static __inline__ void * __attribute__((__always_inline__, __nodebug__))
+__gcspr() {
+ return (void *)__builtin_arm_rsr6
@@ -855,6 +863,25 @@ __rndrrs(uint64_t *__p) {
}
#endif
+/* 11.2 Guarded Control Stack intrinsics */
+#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE
+static __inline__ void * __attribute__((__always_inline__, __nodebug__))
+__gcspr() {
+ return (void *)__builtin_arm_rsr6
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: John Brawn (john-brawn-arm)
Changes
This adds intrinsics defined in ARM-software/acle#260
Doing this requires some changes to the GCS instruction definitions, as these
intrinsics make use of how some instructions don't modify th
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: John Brawn (john-brawn-arm)
Changes
This adds intrinsics defined in ARM-software/acle#260
Doing this requires some changes to the GCS instruction definitions, as these
intrinsics make use of how some instructions don't modify the input re
https://github.com/john-brawn-arm created
https://github.com/llvm/llvm-project/pull/96903
This adds intrinsics defined in ARM-software/acle#260
Doing this requires some changes to the GCS instruction definitions, as these
intrinsics make use of how some instructions don't modify the input regi
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