https://github.com/andykaylor closed
https://github.com/llvm/llvm-project/pull/137106
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@@ -422,6 +428,121 @@ mlir::LogicalResult CIRGenFunction::emitBreakStmt(const
clang::BreakStmt &s) {
return mlir::success();
}
+template
+mlir::LogicalResult
+CIRGenFunction::emitCaseDefaultCascade(const T *stmt, mlir::Type condType,
+
@@ -802,6 +804,126 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -802,6 +804,126 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -422,6 +428,121 @@ mlir::LogicalResult CIRGenFunction::emitBreakStmt(const
clang::BreakStmt &s) {
return mlir::success();
}
+template
+mlir::LogicalResult
+CIRGenFunction::emitCaseDefaultCascade(const T *stmt, mlir::Type condType,
+
@@ -422,6 +428,121 @@ mlir::LogicalResult CIRGenFunction::emitBreakStmt(const
clang::BreakStmt &s) {
return mlir::success();
}
+template
+mlir::LogicalResult
+CIRGenFunction::emitCaseDefaultCascade(const T *stmt, mlir::Type condType,
+
@@ -422,6 +428,121 @@ mlir::LogicalResult CIRGenFunction::emitBreakStmt(const
clang::BreakStmt &s) {
return mlir::success();
}
+template
+mlir::LogicalResult
+CIRGenFunction::emitCaseDefaultCascade(const T *stmt, mlir::Type condType,
+
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -600,3 +721,99 @@ mlir::LogicalResult CIRGenFunction::emitWhileStmt(const
WhileStmt &s) {
terminateBody(builder, whileOp.getBody(), getLoc(s.getEndLoc()));
return mlir::success();
}
+
+mlir::LogicalResult CIRGenFunction::emitSwitchBody(const Stmt *s) {
+ // It is rare
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
https://github.com/Andres-Salamanca updated
https://github.com/llvm/llvm-project/pull/137106
>From f1f56e16d524783c69016867fcdf474ac3e4e09f Mon Sep 17 00:00:00 2001
From: Andres Salamanca
Date: Tue, 22 Apr 2025 15:16:19 -0500
Subject: [PATCH 1/8] Add initial CIR support for switch operation
--
https://github.com/Andres-Salamanca updated
https://github.com/llvm/llvm-project/pull/137106
>From f1f56e16d524783c69016867fcdf474ac3e4e09f Mon Sep 17 00:00:00 2001
From: Andres Salamanca
Date: Tue, 22 Apr 2025 15:16:19 -0500
Subject: [PATCH 1/8] Add initial CIR support for switch operation
--
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -600,3 +721,99 @@ mlir::LogicalResult CIRGenFunction::emitWhileStmt(const
WhileStmt &s) {
terminateBody(builder, whileOp.getBody(), getLoc(s.getEndLoc()));
return mlir::success();
}
+
+mlir::LogicalResult CIRGenFunction::emitSwitchBody(const Stmt *s) {
+ // It is rare
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -422,6 +428,121 @@ mlir::LogicalResult CIRGenFunction::emitBreakStmt(const
clang::BreakStmt &s) {
return mlir::success();
}
+template
+mlir::LogicalResult
+CIRGenFunction::emitCaseDefaultCascade(const T *stmt, mlir::Type condType,
+
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
@@ -600,3 +721,99 @@ mlir::LogicalResult CIRGenFunction::emitWhileStmt(const
WhileStmt &s) {
terminateBody(builder, whileOp.getBody(), getLoc(s.getEndLoc()));
return mlir::success();
}
+
+mlir::LogicalResult CIRGenFunction::emitSwitchBody(const Stmt *s) {
+ // It is rare
@@ -753,6 +755,221 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
https://github.com/Andres-Salamanca updated
https://github.com/llvm/llvm-project/pull/137106
>From f1f56e16d524783c69016867fcdf474ac3e4e09f Mon Sep 17 00:00:00 2001
From: Andres Salamanca
Date: Tue, 22 Apr 2025 15:16:19 -0500
Subject: [PATCH 1/7] Add initial CIR support for switch operation
--
https://github.com/Andres-Salamanca updated
https://github.com/llvm/llvm-project/pull/137106
>From f1f56e16d524783c69016867fcdf474ac3e4e09f Mon Sep 17 00:00:00 2001
From: Andres Salamanca
Date: Tue, 22 Apr 2025 15:16:19 -0500
Subject: [PATCH 1/6] Add initial CIR support for switch operation
--
https://github.com/Andres-Salamanca updated
https://github.com/llvm/llvm-project/pull/137106
>From 22bd39ed8180febabf6e7e742fdfe425ca96c127 Mon Sep 17 00:00:00 2001
From: Andres Salamanca
Date: Tue, 22 Apr 2025 15:16:19 -0500
Subject: [PATCH 1/6] Add initial CIR support for switch operation
--
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
https://github.com/Andres-Salamanca updated
https://github.com/llvm/llvm-project/pull/137106
>From da645e2445e5539e7ea53307596de684203ecd27 Mon Sep 17 00:00:00 2001
From: Andres Salamanca
Date: Tue, 22 Apr 2025 15:16:19 -0500
Subject: [PATCH 1/5] Add initial CIR support for switch operation
--
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
Andres-Salamanca wrote:
@bcardosolopes I've added more test, let me know if there's a specific scenario
you think is still missing
https://github.com/llvm/llvm-project/pull/137106
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@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -753,6 +755,225 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
https://github.com/Andres-Salamanca updated
https://github.com/llvm/llvm-project/pull/137106
>From da645e2445e5539e7ea53307596de684203ecd27 Mon Sep 17 00:00:00 2001
From: Andres Salamanca
Date: Tue, 22 Apr 2025 15:16:19 -0500
Subject: [PATCH 1/4] Add initial CIR support for switch operation
--
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -802,6 +804,132 @@ Block
*cir::BrCondOp::getSuccessorForOperands(ArrayRef operands) {
return nullptr;
}
+//===--===//
+// CaseOp
+//===
@@ -753,6 +755,225 @@ def ScopeOp : CIR_Op<"scope", [
];
}
+//===--===//
+// SwitchOp
+//===--===//
+
+def CaseOpKind_DT : I32EnumAttrCase<
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