DavidSpickett added inline comments.
Comment at: clang/test/CodeGen/aarch64-neon-range-checks.c:31
vsm3tt2bq_u32(a, b, c, 0);
+
+void test_range_check_xar(uint64x2_t a, uint64x2_t b) {
I added a "}" here. Please run ninja check-clang and/or check-llvm before y
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2c25efcbd322: [AArch64] Adding SHA3 Intrinsics support
(authored by rsanthir.quic, committed by DavidSpickett).
Changed prior to commit:
https://reviews.llvm.org/D96381?vs=324711&id=325416#toc
Reposito
rsanthir.quic added a comment.
Thank you for reviewing this @DavidSpickett ! If you get a chance could you
commit this for me? I do not have commit access yet.
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DavidSpickett accepted this revision.
DavidSpickett added a comment.
This revision is now accepted and ready to land.
LGTM
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rsanthir.quic added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:928
+
+class SHA512H_pattern
+ : Pat<(v2i64 (OpNode (v2i64 V128:$Vd), (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
DavidSpickett wrote:
> This is unused.
a good catch thank you
rsanthir.quic updated this revision to Diff 324711.
rsanthir.quic marked 3 inline comments as done.
rsanthir.quic added a comment.
Minor corrections and removed unused code, also added complete testing
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DavidSpickett added a comment.
The approach for xar looks fine to me, matches how we handled vcvt_n_*
(https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcvt_n_).
Comment at: clang/include/clang/Basic/arm_neon.td:1139
+def BCAX : SInst<"
rsanthir.quic updated this revision to Diff 324347.
rsanthir.quic added a comment.
Removed extra whitespace
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clang/include/clang/Basic/arm_neon_incl.
DavidSpickett added a comment.
One nit for now, I'll take a proper look tomorrow. Thanks for your work on
these!
Comment at: clang/test/CodeGen/aarch64-neon-sha3.c:26
+void test_vsha512su0(uint64x2_t w0_1, uint64x2_t w2_) {
+
+ uint64x2_t result = vsha512su0q_u64(w0_1, w2_);
apazos added a comment.
This looks like a straightforward implementation. The only caveat is that the
XAR immediate does not represent a lane, and hence the need for a custom
immediate range check. Looks sensible to me.
@labrinea and others at ARM, do have any other comment before this is merg
rsanthir.quic updated this revision to Diff 322713.
rsanthir.quic added a comment.
alphabetized check in NeonEmitter
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apazos added inline comments.
Comment at: clang/utils/TableGen/NeonEmitter.cpp:2118
Record *R = Def->getRecord();
-if (R->getValueAsBit("isVCVT_N")) {
+if (R->getValueAsBit("isVXAR")) {
+ //VXAR takes an immediate in the range [0, 63]
Consider a
rsanthir.quic added a comment.
This is the second of three patches to address the following:
https://bugs.llvm.org/show_bug.cgi?id=47828
Repository:
rG LLVM Github Monorepo
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rsanthir.quic created this revision.
rsanthir.quic added reviewers: apazos, t.p.northover, labrinea, pbarrio.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
rsanthir.quic requested review of this revision.
Herald added projects: clang, LLVM.
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