[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-13 Thread Amara Emerson via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL307919: [AArch64] Add support for handling the +sve target feature. (authored by aemerson). Changed prior to commit: https://reviews.llvm.org/D35118?vs=106386&id=106432#toc Repository: rL LLVM https

[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-13 Thread Renato Golin via Phabricator via cfe-commits
rengolin accepted this revision. rengolin added a comment. This revision is now accepted and ready to land. Thanks. LGTM. Repository: rL LLVM https://reviews.llvm.org/D35118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-13 Thread Amara Emerson via Phabricator via cfe-commits
aemerson updated this revision to Diff 106386. aemerson added a comment. The reason it's removed is because it's not actually used anywhere, just as a default value. I'm not going to debate it further though so I've put it back in. Repository: rL LLVM https://reviews.llvm.org/D35118 Files:

[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-13 Thread Renato Golin via Phabricator via cfe-commits
rengolin added a comment. In https://reviews.llvm.org/D35118#807712, @aemerson wrote: > In https://reviews.llvm.org/D35118#806730, @rengolin wrote: > > > @jmolloy Can you check this change, please? > > > I'm not really removing FPUMode, I'm just converting an enum to a bit field. > FPUMode, i.e.

[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-13 Thread Amara Emerson via Phabricator via cfe-commits
aemerson added a comment. In https://reviews.llvm.org/D35118#806730, @rengolin wrote: > @jmolloy Can you check this change, please? I'm not really removing FPUMode, I'm just converting an enum to a bit field. FPUMode, i.e. no NEON, after this change is now represented by simply having all bit

[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-12 Thread Renato Golin via Phabricator via cfe-commits
rengolin added a reviewer: jmolloy. rengolin added a subscriber: jmolloy. rengolin added a comment. @jmolloy Can you check this change, please? Comment at: lib/Basic/Targets.cpp:6245 enum FPUModeEnum { -FPUMode, -NeonMode +NeonMode = (1 << 0), +SveMode = (1 <

[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-07 Thread Amara Emerson via Phabricator via cfe-commits
aemerson added inline comments. Comment at: lib/Basic/Targets.cpp:6245 enum FPUModeEnum { -FPUMode, -NeonMode +NeonMode = (1 << 0), +SveMode = (1 << 1) rengolin wrote: > Is there any AArch64 arch without SIMD? > > Anyway, that seems deliberate

[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-07 Thread Renato Golin via Phabricator via cfe-commits
rengolin added a reviewer: t.p.northover. rengolin added a subscriber: t.p.northover. rengolin added inline comments. Comment at: lib/Basic/Targets.cpp:6245 enum FPUModeEnum { -FPUMode, -NeonMode +NeonMode = (1 << 0), +SveMode = (1 << 1) Is the

[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

2017-07-07 Thread Amara Emerson via Phabricator via cfe-commits
aemerson created this revision. aemerson added a project: clang. Herald added subscribers: kristof.beyls, tschuett, javed.absar. [AArch64] Add support for handling the +sve target feature. This also adds the appropriate predefine for SVE if enabled. Depends on https://reviews.llvm.org/D35076 R