[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

SForeKeeper added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:35 +PROC(XIANGSHAN_YANQIHU,{"xiangshan-yanqihu"},FK_64BIT,{"rv64gc"}) +PROC(XIANGSHAN_NANHU,{"xiangshan-nanhu"},FK_64BIT,{"rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed

[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

StephenFan added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:547 +def : ProcessorModel<"xiangshan-nanhu", NoSchedModel, [Feature64Bit, + FeatureStdExtM, + F

[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

jrtc27 added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:34 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"}) +PROC(XIANGSHAN_YANQIHU,{"xiangshan-yanqihu"},FK_64BIT,{"rv64gc"}) +PROC(XIANGSHAN_NANHU,{"xiangshan-nanhu"},FK_64BIT,{"rv64imafdc_

[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

MaskRay added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:146 +// MCPU-XS-NANHU: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-XS-NANHU: "-target-feature" "+c" "-target-feature" "+zba" "-target-feature" "+zb

[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

MaskRay added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-metadata.c:18 +// Test if Xiangshan processors work with -target-cpu +// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - -target-cpu xiangshan-yanqihu %s | FileCheck -check-prefix=EMPTY-LP64 %s -

[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

SForeKeeper created this revision. Herald added subscribers: s, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasa