[PATCH] D109260: [RISCV] Add SiFive core E20

2021-09-03 Thread Alexander Pivovarov via Phabricator via cfe-commits
apivovarov added a comment. Another missing combination is: - e24 and e34 (rocket, rv32imafc) I can also add several cores which are similar to existing cores: - e21 (same as existing e31 - rocket, rv32imac) - s21 (same as existing s51 - rocket, rv64imac) - s54 (same as existing u54 - rocket, r

[PATCH] D109260: [RISCV] Add SiFive core E20

2021-09-03 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added a comment. Are you planning to add more CPUs? I think I'd be willing to accept them all as one patch instead of one small patch for each CPU. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109260/new/ https://reviews.llvm.org/D10

[PATCH] D109260: [RISCV] Add SiFive core E20

2021-09-03 Thread Alexander Pivovarov via Phabricator via cfe-commits
apivovarov created this revision. apivovarov added reviewers: MaskRay, evandro. Herald added subscribers: vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kit