marksl accepted this revision.
marksl added a comment.
This revision is now accepted and ready to land.
Looks good
Repository:
rG LLVM Github Monorepo
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thomasjohns updated this revision to Diff 364855.
thomasjohns added a comment.
Thanks for the feedback, Mark.
This change prefers `MI` over `SI` naming, updates instruction writing, and
makes the test case more precise (the generated code was improved and no longer
had an unneeded `mov %r1, %r0
marksl added inline comments.
Comment at: llvm/lib/Target/ARC/ARCExpandPseudos.cpp:86
+ // %R2 = RSUB_cc_rru6 %R2, 31, pred:2, %STATUS
+ MachineInstr &SI = *SII;
+ const MachineOperand &Dest = SI.getOperand(0);
I know you're following ExpandStore above in us
thomasjohns updated this revision to Diff 364806.
thomasjohns added a comment.
llvm clang-tidy rule: prefer `Register` over `unsinged int`.
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Files:
clang/lib/Basic/Targets/ARC.h
llvm/lib/Targe
thomasjohns updated this revision to Diff 364657.
thomasjohns added a comment.
Fix missing `}` after bad merge. Move CTLZ next to other pseudo instructions.
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Files:
clang/lib/Basic/Targets/ARC.h
thomasjohns added inline comments.
Comment at: llvm/lib/Target/ARC/ARCInstrInfo.td:314
defm NORMH : ArcUnaryEXT5Inst<0b001000,"normh">;
+
+// TODO: Add `Requires<[HasBitScan]>` predicate when available.
thomasjohns wrote:
> I just realized I made a bad merge h
thomasjohns added inline comments.
Comment at: llvm/lib/Target/ARC/ARCInstrInfo.td:314
defm NORMH : ArcUnaryEXT5Inst<0b001000,"normh">;
+
+// TODO: Add `Requires<[HasBitScan]>` predicate when available.
I just realized I made a bad merge here and dropped the `
thomasjohns created this revision.
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Add a CTLZ pseudo instruction to tablegen and the ability to exp
