@@ -33,8 +46,114 @@ static bool CheckAllArgsHaveSameType(Sema *S, CallExpr
*TheCall) {
return false;
}
-bool SemaSPIRV::CheckSPIRVBuiltinFunctionCall(unsigned BuiltinID,
+static std::optional
+processConstant32BitIntArgument(Sema &SemaRef, CallExpr *Call, int Argument) {
+
@@ -97,10 +97,10 @@ static Value *EmitTargetArchBuiltinExpr(CodeGenFunction
*CGF,
case llvm::Triple::riscv64:
return CGF->EmitRISCVBuiltinExpr(BuiltinID, E, ReturnValue);
case llvm::Triple::spirv:
Naghasan wrote:
nope, I fixed it
https://github.com/l
https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/137805
>From 020a804188b13ef881dcf1cbd81a5e11e4803d62 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Mon, 28 Apr 2025 16:20:09 +0100
Subject: [PATCH 1/2] [clang][SPIRV] Add builtin for OpGenericCastToPtrExplicit
@@ -35,8 +35,10 @@ static constexpr Builtin::Info BuiltinInfos[] = {
static_assert(std::size(BuiltinInfos) == NumBuiltins);
llvm::SmallVector
-SPIRVTargetInfo::getTargetBuiltins() const {
- return {{&BuiltinStrings, BuiltinInfos}};
+BaseSPIRTargetInfo::getTargetBuiltins() con
https://github.com/Naghasan edited
https://github.com/llvm/llvm-project/pull/137805
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https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/137805
>From 020a804188b13ef881dcf1cbd81a5e11e4803d62 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Mon, 28 Apr 2025 16:20:09 +0100
Subject: [PATCH 1/2] [clang][SPIRV] Add builtin for OpGenericCastToPtrExplicit
@@ -35,8 +35,10 @@ static constexpr Builtin::Info BuiltinInfos[] = {
static_assert(std::size(BuiltinInfos) == NumBuiltins);
llvm::SmallVector
-SPIRVTargetInfo::getTargetBuiltins() const {
- return {{&BuiltinStrings, BuiltinInfos}};
+BaseSPIRTargetInfo::getTargetBuiltins() con
@@ -5837,12 +5838,13 @@ static void handleBuiltinAliasAttr(Sema &S, Decl *D,
const ParsedAttr &AL) {
bool IsAArch64 = S.Context.getTargetInfo().getTriple().isAArch64();
bool IsARM = S.Context.getTargetInfo().getTriple().isARM();
bool IsRISCV = S.Context.getTargetInfo().g
@@ -35,8 +35,10 @@ static constexpr Builtin::Info BuiltinInfos[] = {
static_assert(std::size(BuiltinInfos) == NumBuiltins);
llvm::SmallVector
-SPIRVTargetInfo::getTargetBuiltins() const {
- return {{&BuiltinStrings, BuiltinInfos}};
+BaseSPIRTargetInfo::getTargetBuiltins() con
@@ -35,8 +35,10 @@ static constexpr Builtin::Info BuiltinInfos[] = {
static_assert(std::size(BuiltinInfos) == NumBuiltins);
llvm::SmallVector
-SPIRVTargetInfo::getTargetBuiltins() const {
- return {{&BuiltinStrings, BuiltinInfos}};
+BaseSPIRTargetInfo::getTargetBuiltins() con
https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/137805
>From 020a804188b13ef881dcf1cbd81a5e11e4803d62 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Mon, 28 Apr 2025 16:20:09 +0100
Subject: [PATCH] [clang][SPIRV] Add builtin for OpGenericCastToPtrExplicit and
https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/137805
>From 90725e8f74295bfd9169e03e73af54c2cf4616ea Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Mon, 28 Apr 2025 16:20:09 +0100
Subject: [PATCH] [clang][SPIRV] Add builtin for OpGenericCastToPtrExplicit and
Naghasan wrote:
Sorry I can't assign reviewers, @JonChesterfield @jhuber6 as you are involved
in gpuintrin.h, I'd welcome feedbacks here (feel free to ping other relevant
persons)
For the SPIR-V side of thing @VyacheslavLevytskyy @farzonl I appreciate your
feedbacks as well :)
FYI @tahoner
https://github.com/Naghasan created
https://github.com/llvm/llvm-project/pull/137805
The patch introduce __builtin_spirv_generic_cast_to_ptr_explicit which is
lowered to the llvm.spv.generic.cast.to.ptr.explicit intrinsic.
The patch also introduces a new header defining its SPIR-V friendly equ
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -92,6 +98,63 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -92,6 +98,63 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
Naghasan wrote:
ping
https://github.com/llvm/llvm-project/pull/94934
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Naghasan wrote:
Still I forgot to answer this point as well...
> Are there ever point releases that might mea +ptx78 should actually expand to
> 780 rather than 78?
not sure what you exactly mean with your question. I guess we can mirror the
cuda arch macro so, major * 100 + minor * 10, no op
https://github.com/Naghasan edited
https://github.com/llvm/llvm-project/pull/94934
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Naghasan wrote:
Thanks for setting the reviewer
> Can you please include rationale for why this this name e.g. why not
> __NVPTX_VERSION__?
`NVPTX` is the name of the LLVM backend, `PTX` is the name of assembly which
have a version hence `__PTX_VERSION__`. Happy to use a better name, but it i
Naghasan wrote:
@Artem-B could you have a look ? I think you are the most relevant for this,
thanks. (Sorry I can't manage assignment)
https://github.com/llvm/llvm-project/pull/94934
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https://github.com/Naghasan created
https://github.com/llvm/llvm-project/pull/94934
Define __PTX_VERSION__ macro to indicate the used PTX version.
Usually each new PTX version brings a new sm version and the associated
instructions. However, some of these instructions can also be made avialabl
@@ -418,8 +418,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final :
public TargetInfo {
// value ~0.
uint64_t getNullPointerValue(LangAS AS) const override {
// FIXME: Also should handle region.
-return (AS == LangAS::opencl_local || AS == LangAS::opencl_pr
@@ -285,6 +289,20 @@ void
NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::GlobalValue *GV,
bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
return false;
}
+
+llvm::Constant *
+NVPTXTargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
+
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