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@@ -6246,40 +6246,178 @@ __m512i test_mm512_ternarylogic_epi32(__m512i __A,
__m512i __B, __m512i __C) {
// CHECK: @llvm.x86.avx512.pternlog.d.512({{.*}}, i32 240)
return _mm512_ternarylogic_epi32(__A, __B, __C, _MM_TERNLOG_A);
}
+TEST_CONSTEXPR(match_v16si(
+ _mm512_terna
@@ -6246,40 +6246,178 @@ __m512i test_mm512_ternarylogic_epi32(__m512i __A,
__m512i __B, __m512i __C) {
// CHECK: @llvm.x86.avx512.pternlog.d.512({{.*}}, i32 240)
return _mm512_ternarylogic_epi32(__A, __B, __C, _MM_TERNLOG_A);
}
+TEST_CONSTEXPR(match_v16si(
+ _mm512_terna
https://github.com/RKSimon approved this pull request.
LGTM - cheers!
https://github.com/llvm/llvm-project/pull/157582
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@@ -2604,6 +2604,52 @@ static bool interp__builtin_elementwise_int_binop(
return true;
}
+static bool
+interp__builtin_x86_pack(InterpState &S, CodePtr, const CallExpr *E,
+ llvm::function_ref PackFn) {
+ const auto *VT0 = E->getArg(0)->getType()->ca
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https://github.com/RKSimon commented:
Thanks @fennecJ this structure looks fine to me - I've added kadd to the
intrinsic list in #158646 as it should be as easy to support as the logic ops
now.
https://github.com/llvm/llvm-project/pull/159998
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@@ -0,0 +1,196 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avxvnniint8
--show-mc-encoding | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-unkno
https://github.com/RKSimon requested changes to this pull request.
The __v16qi/__v32qi/___v64qi types inside the TEST_CONSTEXPR need converting to
__v16qs/__v32qs/___v64qs - sorry my script didn't handle this :/
https://github.com/llvm/llvm-project/pull/157582
_
@@ -41,15 +51,18 @@ __m256 test_mm256_cvtph_ps(__m128i a) {
// CHECK: fpext <8 x half> %{{.*}} to <8 x float>
return _mm256_cvtph_ps(a);
}
+TEST_CONSTEXPR(match_m256(
+_mm256_cvtph_ps(_mm_setr_epi16(0x3C00, 0x4000, 0x4200, 0x4400, 0x4500,
0x3800, 0xC000, 0x)),
+
https://github.com/RKSimon created
https://github.com/llvm/llvm-project/pull/157681
Extends interp__builtin_elementwise_triop to handle (vector, vector, scalar)
trinary op intrinsics
Fixes #153152
>From d690a70f21e7ac309ca5acab843e75b54e71c4a4 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim
Dat
@@ -2060,7 +2060,7 @@ static __inline__ void __DEFAULT_FN_ATTRS
_mm_storel_pd(double *__dp,
///A 128-bit vector of [16 x i8].
/// \returns A 128-bit vector of [16 x i8] containing the sums of both
///parameters.
-static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_add_epi
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https://github.com/RKSimon updated
https://github.com/llvm/llvm-project/pull/158020
>From be9cd0cf8feb76b2de4e9ab095580802a5989071 Mon Sep 17 00:00:00 2001
From: kimsh02
Date: Thu, 11 Sep 2025 01:39:06 -0700
Subject: [PATCH 1/2] [Headers][X86] Allow AVX vector concatenation intrinsics
to be us
@@ -0,0 +1,87 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux-gnu -O0
-target-cpu skylake-avx512 -std=c++17 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux-gnu -O0
-target-cp
https://github.com/RKSimon updated
https://github.com/llvm/llvm-project/pull/157776
>From 019b3ba36b8205b57135ab22b4603fee7d453945 Mon Sep 17 00:00:00 2001
From: Brandon Xin
Date: Tue, 9 Sep 2025 19:26:11 -0500
Subject: [PATCH 1/7] [X86][bytecode] Allow SSE/AVX BLEND imm intrinsics to be
used
@@ -2604,6 +2605,65 @@ static bool interp__builtin_elementwise_int_binop(
return true;
}
+static bool interp__builtin_x86_pack(
+InterpState &S, CodePtr, const CallExpr *E, bool IsUnsat,
+llvm::function_ref
+narrowElement) {
+ const auto *VT0 = E->getArg(0)-
@@ -24,6 +24,7 @@ typedef float __m128_u __attribute__((__vector_size__(16),
__aligned__(1)));
/* Unsigned types */
typedef unsigned int __v4su __attribute__((__vector_size__(16)));
typedef unsigned short __v8hu __attribute__((__vector_size__(16)));
+typedef unsigned char __v1
https://github.com/RKSimon created
https://github.com/llvm/llvm-project/pull/157668
Now that they wrap the __builtin_elementwise_fshl/fshr builtin intrinsics this
is pretty trivial.
Just one more step towards #153152 - just VBMI2 funnel shifts by immediate
>From e16db4cb34c179f8cbecc8990d9399
https://github.com/RKSimon updated
https://github.com/llvm/llvm-project/pull/157681
>From d690a70f21e7ac309ca5acab843e75b54e71c4a4 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim
Date: Tue, 9 Sep 2025 15:25:54 +0100
Subject: [PATCH] [clang][bytecode][X86] Allow AVX512 funnel shift by scalar
immed
https://github.com/RKSimon requested changes to this pull request.
please can you merge against trunk
https://github.com/llvm/llvm-project/pull/158703
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@@ -3477,6 +3523,30 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC,
const CallExpr *Call,
}
return LHS.lshr(RHS.getZExtValue());
});
+ case clang::X86::BI__builtin_ia32_packsswb128:
+ case clang::X86::BI__builtin_ia32_packsswb256:
+ case c
RKSimon wrote:
> @RKSimon from what I can see in clang/lib/Headers/mmintrin.h, it looks like
> all the intrinsics you mentioned are already being used in CONSTEXPR, shall I
> make test cases for it?
Ah! I forgot I'd done these ages ago - they should already have test coverage
if I did it prop
@@ -464,36 +464,60 @@ __m256i test_mm256_hadd_epi16(__m256i a, __m256i b) {
// CHECK: call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %{{.*}}, <16 x
i16> %{{.*}})
return _mm256_hadd_epi16(a, b);
}
+TEST_CONSTEXPR(match_v16hi(_mm256_hadd_epi16(
+(__m256i)(__v16hi){1,2
@@ -12192,67 +12332,71 @@ bool
VectorExprEvaluator::VisitShuffleVectorExpr(const ShuffleVectorExpr *E) {
namespace {
class ArrayExprEvaluator
- : public ExprEvaluatorBase {
-const LValue &This;
-APValue &Result;
- public:
-
-ArrayExprEvaluator(EvalInfo &Info,
@@ -3453,6 +3592,30 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC,
const CallExpr *Call,
case Builtin::BI__builtin_elementwise_min:
return interp__builtin_elementwise_maxmin(S, OpPC, Call, BuiltinID);
+ case clang::X86::BI__builtin_ia32_phaddw128:
+ case clang
https://github.com/RKSimon requested changes to this pull request.
Please can you handle the MMX intrinsics as well?
```
_mm_add_pi8 _mm_add_pi16 _mm_add_pi32
_mm_sub_pi8 _mm_sub_pi16 _mm_sub_pi32
```
https://github.com/llvm/llvm-project/pull/157582
__
RKSimon wrote:
@donneypr I've been playing with a script to help autogen the tests as that
seems to be bottleneck for people - see if these work OK (they still need
putting in the correct builtins files):
```
TEST_CONSTEXPR(match_v16qi(_mm_add_epi8((__m128i)(__v16qi){ 32, 33, 34, -35,
-36, -37
@@ -11575,6 +11575,43 @@ static bool handleVectorElementCast(EvalInfo &Info,
const FPOptions FPO,
return false;
}
+static bool
+evalPackBuiltin(const CallExpr *E, EvalInfo &Info, APValue &Result,
+llvm::function_ref narrowElement) {
RKSimon
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@@ -2604,6 +2605,51 @@ static bool interp__builtin_elementwise_int_binop(
return true;
}
+static bool interp__builtin_x86_pack(
+InterpState &S, CodePtr, const CallExpr *E,
+llvm::function_ref narrowElement) {
RKSimon wrote:
narrowElement -> PackFn?
@@ -3453,6 +3592,30 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC,
const CallExpr *Call,
case Builtin::BI__builtin_elementwise_min:
return interp__builtin_elementwise_maxmin(S, OpPC, Call, BuiltinID);
+ case clang::X86::BI__builtin_ia32_phaddw128:
+ case clang
@@ -8,6 +8,7 @@
#include "../ExprConstShared.h"
#include "Boolean.h"
#include "EvalEmitter.h"
+#include "Floating.h"
RKSimon wrote:
unnecessary?
https://github.com/llvm/llvm-project/pull/156822
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@@ -19,6 +20,7 @@
#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/SipHash.h"
+#include
RKSimon wrote:
unnecessary?
https://github.com/llvm/llvm-project/pull/156822
https://github.com/RKSimon requested changes to this pull request.
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https://github.com/RKSimon approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/157128
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https://github.com/RKSimon requested changes to this pull request.
Needs the avxvnniint8 intrinsics upgrade tests moving to
avxvnniint8-intrinsics-upgrade.ll
https://github.com/llvm/llvm-project/pull/159222
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@@ -2607,3 +2607,19 @@ void test_mm512_mask_cvtusepi16_storeu_epi8 (void * __P,
__mmask32 __M, __m512i
// CHECK: @llvm.x86.avx512.mask.pmovus.wb.mem.512
_mm512_mask_cvtusepi16_storeu_epi8 ( __P, __M, __A);
}
+
+__m512i test_mm512_bslli_epi16(__m512i a) {
+ // CHECK-LABEL: @
@@ -2607,3 +2607,19 @@ void test_mm512_mask_cvtusepi16_storeu_epi8 (void * __P,
__mmask32 __M, __m512i
// CHECK: @llvm.x86.avx512.mask.pmovus.wb.mem.512
_mm512_mask_cvtusepi16_storeu_epi8 ( __P, __M, __A);
}
+
+__m512i test_mm512_bslli_epi16(__m512i a) {
+ // CHECK-LABEL: @
@@ -2607,3 +2607,19 @@ void test_mm512_mask_cvtusepi16_storeu_epi8 (void * __P,
__mmask32 __M, __m512i
// CHECK: @llvm.x86.avx512.mask.pmovus.wb.mem.512
_mm512_mask_cvtusepi16_storeu_epi8 ( __P, __M, __A);
}
+
+__m512i test_mm512_bslli_epi16(__m512i a) {
+ // CHECK-LABEL: @
@@ -318,17 +318,25 @@ let Features = "sse4.1", Attributes = [NoThrow, Const,
RequiredVectorWidth<128>]
def roundsd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2,
double>, _Constant int)">;
def roundpd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _C
@@ -12025,6 +12025,56 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
+ case X86::BI__builtin_ia32_ptestz128: {
RKSimon wrote:
won't this need to be in IntExpr
https://github.com/RKSimon updated
https://github.com/llvm/llvm-project/pull/156234
>From d4bd99d0d164e25eb2fdaf3899fb1b24734807de Mon Sep 17 00:00:00 2001
From: notnotharsh
Date: Sun, 31 Aug 2025 03:03:34 -0700
Subject: [PATCH 1/3] [Headers][X86] Allow AVX512 masked blend intrinsics to be
use
@@ -2937,6 +2937,50 @@ static bool interp__builtin_elementwise_triop(
return true;
}
+static bool interp__builtin_x86_insert_subvector(InterpState &S, CodePtr OpPC,
+ const CallExpr *Call,
+
https://github.com/RKSimon updated
https://github.com/llvm/llvm-project/pull/159231
>From 55d9d6064836c78d8c982a81b0ad24ffbfb9ff83 Mon Sep 17 00:00:00 2001
From: sskzakaria
Date: Fri, 12 Sep 2025 18:06:50 -0400
Subject: [PATCH 01/11] _mm256_cvtepu16_ph
---
clang/lib/Headers/avx512vlfp16intrin
https://github.com/RKSimon approved this pull request.
LGTM - cheers
https://github.com/llvm/llvm-project/pull/158663
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@@ -2914,6 +2914,47 @@ static bool interp__builtin_elementwise_triop(
return true;
}
+static bool interp__builtin_x86_insert_subvector(InterpState &S, CodePtr OpPC,
+ const CallExpr *Call,
+
@@ -3435,6 +3524,22 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC,
const CallExpr *Call,
}
return LHS.lshr(RHS.getZExtValue());
});
+ case clang::X86::BI__builtin_ia32_packsswb128:
+ case clang::X86::BI__builtin_ia32_packsswb256:
+ case c
https://github.com/RKSimon edited
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RKSimon wrote:
At the moment we need to keep _mm_mask_cvtepi16_epi8 etc as the selection mask
only acts on part of the vector (we're truncating v8i16 to v8i8, using the
mask8 on that and passing through all the upper half of the passthrough to
create a v16i8) - the best we might be able to do
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https://github.com/RKSimon approved this pull request.
LGTM - cheers
https://github.com/llvm/llvm-project/pull/158778
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https://github.com/RKSimon updated
https://github.com/llvm/llvm-project/pull/158778
>From 491504e0c58087ad44dbc7be039e95658c444a82 Mon Sep 17 00:00:00 2001
From: AdityaC4
Date: Mon, 15 Sep 2025 23:19:21 -0500
Subject: [PATCH 1/7] [Clang] VectorExprEvaluator::VisitCallExpr /
InterpretBuiltin -
@@ -12127,6 +12127,49 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
+ case X86::BI__builtin_ia32_pslldqi128_byteshift:
+ case X86::BI__builtin_ia32_psrldqi128_byteshift:
+ c
@@ -12127,6 +12127,49 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
+ case X86::BI__builtin_ia32_pslldqi128_byteshift:
+ case X86::BI__builtin_ia32_psrldqi128_byteshift:
+ c
https://github.com/RKSimon edited
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https://github.com/RKSimon requested changes to this pull request.
Make use of your callback functions already known what form of pack instruction
they use - no need to pass in usat / bitwidth etc. in.
https://github.com/llvm/llvm-project/pull/156003
@@ -2604,6 +2605,65 @@ static bool interp__builtin_elementwise_int_binop(
return true;
}
+static bool interp__builtin_x86_pack(
+InterpState &S, CodePtr, const CallExpr *E, bool IsUnsat,
+llvm::function_ref
+narrowElement) {
+ const auto *VT0 = E->getArg(0)-
@@ -3435,6 +3524,22 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC,
const CallExpr *Call,
}
return LHS.lshr(RHS.getZExtValue());
});
+ case clang::X86::BI__builtin_ia32_packsswb128:
+ case clang::X86::BI__builtin_ia32_packsswb256:
+ case c
https://github.com/RKSimon requested changes to this pull request.
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@@ -0,0 +1,291 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx10.2
--show-mc-encoding | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-u
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https://github.com/RKSimon approved this pull request.
LGTM - cheers
https://github.com/llvm/llvm-project/pull/159231
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https://github.com/RKSimon created
https://github.com/llvm/llvm-project/pull/157696
Handle missing AVX512F epi64 and AVX512BW epi16 cases with existing code paths
Fixes #154287
>From f1e59ef0d2f1cf8ef454df64f98a10658edf48b2 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim
Date: Tue, 9 Sep 2025 16
https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/157403
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RKSimon wrote:
> The libc++ part LGTM.
Any advice on the libcxx buildbot CI failures?
https://github.com/llvm/llvm-project/pull/158048
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@@ -690,50 +690,40 @@ _mm512_maskz_adds_epu16 (__mmask32 __U, __m512i __A,
__m512i __B)
(__v32hi)_mm512_setzero_si512());
}
-static __inline__ __m512i __DEFAULT_FN_ATTRS512
-_mm512_avg_epu8 (__m512i __A, __m512i __B)
-{
- return (__m51
RKSimon wrote:
@abhinavp5 Make sure you don't update again or the auto-merge will fail
https://github.com/llvm/llvm-project/pull/158142
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@@ -1305,11 +1306,14 @@ let Features = "avx512f", Attributes = [NoThrow, Const,
RequiredVectorWidth<512>
let Features = "avx512bw", Attributes = [NoThrow, Const,
RequiredVectorWidth<512>] in {
def ucmpw512_mask : X86Builtin<"unsigned int(_Vector<32, short>, _Vector<32,
sh
@@ -2604,6 +2604,68 @@ static bool interp__builtin_elementwise_int_binop(
return true;
}
+static bool interp__builtin_x86_pack(
+InterpState &S, CodePtr, const CallExpr *E, unsigned SrcBits, bool IsUnsat,
+llvm::function_ref
+narrowElement) {
@@ -2604,6 +2604,68 @@ static bool interp__builtin_elementwise_int_binop(
return true;
}
+static bool interp__builtin_x86_pack(
+InterpState &S, CodePtr, const CallExpr *E, unsigned SrcBits, bool IsUnsat,
+llvm::function_ref
+narrowElement) {
+ const auto *V
https://github.com/RKSimon requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/156003
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@@ -12127,6 +12127,55 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
+
+ case X86::BI__builtin_ia32_insertf32x4_256:
+ case X86::BI__builtin_ia32_inserti32x4_256:
+ case X86:
@@ -513,6 +510,12 @@ let Features = "avx", Attributes = [NoThrow, Const,
RequiredVectorWidth<256>] in
def roundps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Constant
int)">;
}
+let Features = "avx", Attributes = [NoThrow, Const, Constexpr,
RequiredVectorWidth<
@@ -12127,6 +12127,55 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
+
+ case X86::BI__builtin_ia32_insertf32x4_256:
+ case X86::BI__builtin_ia32_inserti32x4_256:
+ case X86:
@@ -0,0 +1,87 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux-gnu -O0
-target-cpu skylake-avx512 -std=c++17 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux-gnu -O0
-target-cp
https://github.com/RKSimon requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/158778
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@@ -609,6 +612,9 @@ let Features = "avx2", Attributes = [NoThrow, Const,
RequiredVectorWidth<256>] i
def permti256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long
int>, _Vector<4, long long int>, _Constant int)">;
def permdi256 : X86Builtin<"_Vector<4, long lo
@@ -2831,6 +2831,44 @@ static bool interp__builtin_select(InterpState &S,
CodePtr OpPC,
return true;
}
+static bool interp__builtin_blend(InterpState &S, CodePtr OpPC,
+ const CallExpr *Call, unsigned BuiltinID) {
+ PrimType MaskT = *S.getC
https://github.com/RKSimon updated
https://github.com/llvm/llvm-project/pull/157403
>From 38b90ecc3dc30668860cc80a6c8f075536764b5e Mon Sep 17 00:00:00 2001
From: kimyounhoex1
Date: Thu, 4 Sep 2025 00:55:24 +0900
Subject: [PATCH 01/12] todo list
---
clang/lib/AST/ExprConstant.cpp | 4
1 f
RKSimon wrote:
@kimyounhoex1 I've merged trunk latest into this patch so that the byteshift
builtins now use vXi8 types - #158671
https://github.com/llvm/llvm-project/pull/157403
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https://github.com/RKSimon closed
https://github.com/llvm/llvm-project/pull/158671
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https://github.com/RKSimon created
https://github.com/llvm/llvm-project/pull/158671
As noted on #156494 and #157403 - its much easier to work with the byte shift
intrinsics if we treat them as vXi8 types instead of vXi64 types which will
require bitcasting
We already do this for the PALIGNR i
https://github.com/RKSimon approved this pull request.
LGTM - cheers
https://github.com/llvm/llvm-project/pull/156234
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@@ -11592,7 +11592,10 @@ static bool handleVectorElementCast(EvalInfo &Info,
const FPOptions FPO,
<< SourceTy << DestTy;
return false;
}
-
+// i should emplement SLLDQ, SRLDQ shift (intrinsics) in constant expression
+// handling inside this function
+// avx2intrin.h -
@@ -12034,6 +12037,46 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
+ case X86::BI__builtin_ia32_pslldqi128_byteshift:
+ case X86::BI__builtin_ia32_psrldqi128_byteshift:
+ c
https://github.com/RKSimon requested changes to this pull request.
You still need to add InterpBuiltin handling, declare the byteshift builtins as
Constexpr in BuiltinsX86.td, add avx512bw-builtins.c test coverage and add
tests that check the 'ShiftVal > 15 case).
https://github.com/llvm/llvm-
https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/157403
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https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/157403
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