https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/159702
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@@ -1431,7 +1431,7 @@ def int_amdgcn_make_buffer_rsrc : DefaultAttrsIntrinsic <
[llvm_anyptr_ty],
[llvm_anyptr_ty, // base
llvm_i16_ty,// stride (and swizzle control)
- llvm_i32_ty,// NumRecords / extent
+ llvm_i64_ty,// NumRecords / extent
--
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/159702
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@@ -11602,29 +11602,48 @@ SDValue
SITargetLowering::lowerPointerAsRsrcIntrin(SDNode *Op,
SDValue NumRecords = Op->getOperand(3);
SDValue Flags = Op->getOperand(4);
- auto [LowHalf, HighHalf] = DAG.SplitScalar(Pointer, Loc, MVT::i32, MVT::i32);
- SDValue Mask = DAG.getCo
@@ -1431,7 +1431,7 @@ def int_amdgcn_make_buffer_rsrc : DefaultAttrsIntrinsic <
[llvm_anyptr_ty],
[llvm_anyptr_ty, // base
llvm_i16_ty,// stride (and swizzle control)
- llvm_i32_ty,// NumRecords / extent
+ llvm_i64_ty,// NumRecords / extent
--
@@ -5905,33 +5905,64 @@ bool AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(
Register Flags = MI.getOperand(5).getReg();
LLT S32 = LLT::scalar(32);
+ LLT S64 = LLT::scalar(64);
B.setInsertPt(B.getMBB(), ++B.getInsertPt());
- auto Unmerge = B.buildUnmerge(S32, Poin
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/157900
>From d7ea946ada63b8ff0a29cc33721ebbd7d5765dec Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 10 Sep 2025 12:56:57 -0400
Subject: [PATCH] [AMDGPU] Change `scale_sel` to be 4 bits
The latest SP changes u
shiltian wrote:
no test?
https://github.com/llvm/llvm-project/pull/158145
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/159430
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shiltian wrote:
I'm not sure what this PR is trying to fix, but we do have type enforcement in
`clang/include/clang/Basic/BuiltinsAMDGPU.def`?
https://github.com/llvm/llvm-project/pull/158145
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htt
shiltian wrote:
@rampitec SP3 has been updated.
https://github.com/llvm/llvm-project/pull/157900
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@@ -1562,6 +1562,23 @@ def HIPManaged : InheritableAttr {
let Documentation = [HIPManagedAttrDocs];
}
+def CUDAClusterDims : InheritableAttr {
+ let Spellings = [GNU<"cluster_dims">, Declspec<"__cluster_dims__">];
+ let Args = [ExprArgument<"X">, ExprArgument<"Y", 1>, Expr
@@ -7532,6 +7532,25 @@ A managed variable can be accessed in both device and
host code.
}];
}
+def CUDAClusterDimsAttrDoc : Documentation {
+ let Category = DocCatDecl;
+ let Content = [{
+In CUDA/HIP programming, the ``__cluster_dims__`` attribute can be applied to
a ke
@@ -843,7 +857,8 @@ void CGOpenMPRuntimeGPU::emitTargetOutlinedFunction(
assert(!ParentName.empty() && "Invalid target region parent name!");
bool Mode = supportsSPMDExecutionMode(CGM.getContext(), D);
- if (Mode)
+ bool IsBareKernel = D.getSingleClause();
+ if (Mode ||
shiltian wrote:
* **#157877** https://app.graphite.dev/github/pr/llvm/llvm-project/157877?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/157
@@ -5654,6 +5654,130 @@ static void handleLaunchBoundsAttr(Sema &S, Decl *D,
const ParsedAttr &AL) {
AL.getNumArgs() > 2 ? AL.getArgAsExpr(2) : nullptr);
}
+static std::pair
+makeClusterDimsArgExpr(Sema &S, Expr *E, const CUDAClusterDimsAttr &AL,
+
shiltian wrote:
> Any tests for intrinsics?
Do you mean the lowering of the intrinsics?
https://github.com/llvm/llvm-project/pull/157877
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/156686
>From 714faa21598f83a2076d546cf1ad81d913a3862a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 3 Sep 2025 10:47:52 -0400
Subject: [PATCH 1/3] [Clang][HIP][CUDA] Add `__cluster_dims__` and
`__no_cluster__
@@ -7532,6 +7532,25 @@ A managed variable can be accessed in both device and
host code.
}];
}
+def CUDAClusterDimsAttrDoc : Documentation {
+ let Category = DocCatDecl;
+ let Content = [{
+In CUDA/HIP programming, the ``__cluster_dims__`` attribute can be applied to
a ke
https://github.com/shiltian closed
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https://github.com/llvm/llvm-project/pull/157900
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shiltian wrote:
That will be in a follow-up PR.
https://github.com/llvm/llvm-project/pull/157877
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@@ -7532,6 +7532,25 @@ A managed variable can be accessed in both device and
host code.
}];
}
+def CUDAClusterDimsAttrDoc : Documentation {
+ let Category = DocCatDecl;
+ let Content = [{
+In CUDA/HIP programming, the ``__cluster_dims__`` attribute can be applied to
a ke
@@ -1557,6 +1557,23 @@ def HIPManaged : InheritableAttr {
let Documentation = [HIPManagedAttrDocs];
}
+def CUDAClusterDims : InheritableAttr {
+ let Spellings = [GNU<"cluster_dims">, Declspec<"__cluster_dims__">];
shiltian wrote:
This is to follow all exis
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/157877
Co-authored-by: Ivan Kosarev
>From 0255f4e61cf3c98e167c29c5fd5aa9ddfb9f1f54 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 10 Sep 2025 11:23:18 -0400
Subject: [PATCH] [AMDGPU] Add builtins and intrinsi
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/157463
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@@ -4734,6 +4734,65 @@ void x() {
EXPECT_TRUE(matchesWithOpenMP(Source8, Matcher));
}
+TEST_P(ASTMatchersTest, OMPTargetUpdateDirective_IsStandaloneDirective) {
+ auto Matcher = ompTargetUpdateDirective(isStandaloneDirective());
+
+ StringRef Source0 = R"(
+void foo()
@@ -20,6 +20,27 @@
using namespace clang;
using namespace llvm::omp;
+unsigned clang::getOpenMPDefaultVariableCategory(StringRef Str,
+ const LangOptions &LangOpts) {
+ unsigned VC = llvm::StringSwitch(Str)
+#define OPENMP_DEFAU
@@ -257,6 +264,10 @@ struct OMPInteropInfo final {
llvm::SmallVector PreferTypes;
};
+unsigned getOpenMPDefaultVariableCategory(StringRef Str,
+ const LangOptions &LangOpts);
+const char *getOpenMPDefaultVariableCategoryName(unsigned
@@ -7532,6 +7532,25 @@ A managed variable can be accessed in both device and
host code.
}];
}
+def CUDAClusterDimsAttrDoc : Documentation {
+ let Category = DocCatDecl;
+ let Content = [{
+In CUDA/HIP programming, the ``__cluster_dims__`` attribute can be applied to
a ke
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/156686
>From 2a30ef5a778fd4aee5ef5f10066ed3bda317e9d1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 3 Sep 2025 10:47:52 -0400
Subject: [PATCH 1/2] [Clang][HIP][CUDA] Add `__cluster_dims__` and
`__no_cluster__
@@ -2742,6 +2742,32 @@ void x() {
EXPECT_TRUE(notMatchesWithOpenMP(Source2, Matcher));
}
+TEST(ASTMatchersTestOpenMP, OMPTargetUpdateDirective) {
+ auto Matcher = stmt(ompTargetUpdateDirective());
+
+ StringRef Source0 = R"(
+void foo() {
+ int arr[8];
+ #pra
@@ -7532,6 +7532,25 @@ A managed variable can be accessed in both device and
host code.
}];
}
+def CUDAClusterDimsAttrDoc : Documentation {
+ let Category = DocCatDecl;
+ let Content = [{
+In CUDA/HIP programming, the ``__cluster_dims__`` attribute can be applied to
a ke
shiltian wrote:
> It isn't clear what these are, why/whether we want them, what their signature
> is, etc.
It is the support for [`__cluster_dims__`
attribute](https://docs.nvidia.com/cuda/cuda-c-programming-guide/#thread-block-clusters).
> Additionally, we do not allow adding undocumented at
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/156686
>From 190dd7af733563bdb99ec5d4812226b86448f273 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 3 Sep 2025 10:47:52 -0400
Subject: [PATCH] [Clang][HIP][CUDA] Add `__cluster_dims__` and
`__no_cluster__` at
Author: Shilei Tian
Date: 2025-09-03T10:51:08-04:00
New Revision: d25d8309d173f81bc26babf9964d4d021b76a4af
URL:
https://github.com/llvm/llvm-project/commit/d25d8309d173f81bc26babf9964d4d021b76a4af
DIFF:
https://github.com/llvm/llvm-project/commit/d25d8309d173f81bc26babf9964d4d021b76a4af.diff
L
shiltian wrote:
* **#156686** https://app.graphite.dev/github/pr/llvm/llvm-project/156686?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/156
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/156686
This PR adds basic frontend support for `__cluster_dims__` and `__no_cluster__`
attribute.
Co-authored-by: Yaxun (Sam) Liu
Co-authored-by: Jay Foad
>From 4d6e3098540bc655b12374d7ac7d0fa13cccbec3 Mon Sep 17
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/156418
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@@ -145,6 +154,50 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
return false;
}
+bool SemaAMDGPU::checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore) {
+ bool Fail = false;
+
+ // First argument is a global or generic pointer.
+ Expr *Pt
@@ -0,0 +1,51 @@
+
+// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=60 -DOMP60 %s
-Wuninitialized
+
+// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=60 -DOMP60 %s
-Wuninitialized
+
+// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -DOMP52 %s
-Wuninitialize
shiltian wrote:
Looking at this now, it doesn't seem the same as it was at the start. For the
latest changes, I think @arsenm made it clear that waves-per-eu values should
always give way to the values calculated from flat-workgroup-size if they
differ, since flat-workgroup-size is ABI and wav
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/155478
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https://github.com/shiltian approved this pull request.
The title needs to be more specific.
https://github.com/llvm/llvm-project/pull/155138
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https://github.com/shiltian commented:
Has `dyn_groupprivate` already been approved to be in 6.1 or is this just a PoC
implementation?
https://github.com/llvm/llvm-project/pull/152651
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https://github.com/llvm/llvm-project/pull/152651
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/153680
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@@ -159,6 +159,119 @@ Value *EmitAMDGPUGridSize(CodeGenFunction &CGF, unsigned
Index) {
llvm::MDNode::get(CGF.getLLVMContext(), {}));
return LD;
}
+// Lowers __builtin_amdgcn_ds_bpermute to the corresponding LLVM intrinsic with
+// careful bit-level coercio
@@ -159,6 +159,119 @@ Value *EmitAMDGPUGridSize(CodeGenFunction &CGF, unsigned
Index) {
llvm::MDNode::get(CGF.getLLVMContext(), {}));
return LD;
}
+// Lowers __builtin_amdgcn_ds_bpermute to the corresponding LLVM intrinsic with
+// careful bit-level coercio
@@ -18,6 +18,132 @@
#include "llvm/Support/AtomicOrdering.h"
#include
+namespace {
+
+using llvm::StringRef;
+using namespace clang;
+
+/// Attempts to apply a user-defined conversion on Arg at ArgIndex to a
+/// 32-bit-compatible type. If successful, updates TheCall's argume
https://github.com/shiltian deleted
https://github.com/llvm/llvm-project/pull/153501
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@@ -159,6 +159,119 @@ Value *EmitAMDGPUGridSize(CodeGenFunction &CGF, unsigned
Index) {
llvm::MDNode::get(CGF.getLLVMContext(), {}));
return LD;
}
+// Lowers __builtin_amdgcn_ds_bpermute to the corresponding LLVM intrinsic with
+// careful bit-level coercio
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/151964
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/135079
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/151058
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shiltian wrote:
FWIW, https://github.com/llvm/llvm-project/pull/143058 seems like doing the
same thing.
https://github.com/llvm/llvm-project/pull/138294
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https://github.com/shiltian approved this pull request.
Is clang tools always installed?
https://github.com/llvm/llvm-project/pull/150965
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https://github.com/shiltian commented:
it doesn't seem to be tested?
https://github.com/llvm/llvm-project/pull/150580
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/150493
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/148627
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shiltian wrote:
I don't know which one. My PRs yesterday afternoon have a lot of crash in ADT
but after rebase a couple of hours later they were gone. I suppose that would
be the one.
https://github.com/llvm/llvm-project/pull/125556
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shiltian wrote:
Someone else messed up it. The commit has been reverted.
https://github.com/llvm/llvm-project/pull/125556
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149684
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149528
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149528
>From 3fb65bcda47f66a47c8295e04102a3a1d675dbd7 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:36:56 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sat_pk4_i4_[i8,u8]` on gfx1250
Co-au
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https://github.com/llvm/llvm-project/pull/149528
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From d58f9605434bfc4de1820f7c6beabd82586a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From f7c11e672cebd2488582ee89e66d9777182db1e1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From e6d5fd17af108d454e43a6489eb7580bf007a170 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 8f89191a1714b2e891eda67d844d32be2ccfc27a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 1d045407b88bc8efae91410223e8ba980cdec6d1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 4d850d602b45130ae958776cd353512116bd5862 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
shiltian wrote:
### Merge activity
* **Jul 18, 4:46 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149518).
https://github.com/llvm/llvm-project/pull/149518
___
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https://github.com/llvm/llvm-project/pull/149518
>From 33991acfd14b041071d112de032afe94c6bedf35 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149518
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https://github.com/llvm/llvm-project/pull/149450
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https://github.com/llvm/llvm-project/pull/149518
>From 345d4d9de11d21c1b087cdf88de22f0d90a7ba9f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
shiltian wrote:
### Merge activity
* **Jul 18, 2:58 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149450).
https://github.com/llvm/llvm-project/pull/149450
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@@ -4007,7 +4007,8 @@ SDValue
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
case Intrinsic::amdgcn_rcp_legacy:
case Intrinsic::amdgcn_rsq_legacy:
case Intrinsic::amdgcn_rsq_clamp:
- case Intrinsic::amdgcn_tanh: {
+ case Intrinsic::amdgcn_tanh:
+ case Intrinsic
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149450
>From e35cd5506ed733fcb62eab4c28ab4e9f5966216f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 00:26:15 -0400
Subject: [PATCH 1/2] [AMDGPU] Add support for `v_prng_b32` on gfx1250
Co-authored
@@ -4007,7 +4007,8 @@ SDValue
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
case Intrinsic::amdgcn_rcp_legacy:
case Intrinsic::amdgcn_rsq_legacy:
case Intrinsic::amdgcn_rsq_clamp:
- case Intrinsic::amdgcn_tanh: {
+ case Intrinsic::amdgcn_tanh:
+ case Intrinsic
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149450
>From e35cd5506ed733fcb62eab4c28ab4e9f5966216f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 00:26:15 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_prng_b32` on gfx1250
Co-authored-by:
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149450
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149447
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shiltian wrote:
### Merge activity
* **Jul 18, 12:42 PM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149447).
https://github.com/llvm/llvm-project/pull/149447
__
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149360
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149360
>From 10b9379f759506e4e1e3c1cab1191ed386609ebe Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 13:03:14 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_f32` on gfx1250
Co-authored-by:
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149360
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149355
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shiltian wrote:
### Merge activity
* **Jul 17, 6:41 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149355).
https://github.com/llvm/llvm-project/pull/149355
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https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149355
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shiltian wrote:
Oh nice catch. Thanks.
https://github.com/llvm/llvm-project/pull/149355
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shiltian wrote:
but we do have `v_cos_bf16` in `llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s`?
https://github.com/llvm/llvm-project/pull/149355
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149355
>From 29b54575b3e64372750466dfafab971697f402f1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 12:45:33 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16_e64` on gfx1250
Co-authored
shiltian wrote:
* **#149355** https://app.graphite.dev/github/pr/llvm/llvm-project/149355?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/149
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149355
Co-authored-by: Mekhanoshin, Stanislav
>From a6b7ccf491c4d88b18bfdba0dbf839030df189ec Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 12:45:33 -0400
Subject: [PATCH] [AMDGPU] Add support for
@@ -610,7 +610,7 @@ void StmtPrinter::VisitObjCAtTryStmt(ObjCAtTryStmt *Node) {
}
}
- if (auto *FS = static_cast(Node->getFinallyStmt())) {
+ if (auto *FS = Node->getFinallyStmt()) {
shiltian wrote:
If there is no cast, then we'd want to use the type
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149338
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149340
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