https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/120061
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LGTM
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LGTM
https://github.com/llvm/llvm-project/pull/113402
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KanRobert wrote:
Passed the validation of cpu2017 on intel sde w/ this patch + APX features.
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>From 88cbdf9765e42dee7d2b050dcf8a20a08b4b148f Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/8] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
KanRobert wrote:
Ping @MaskRay ?
https://github.com/llvm/llvm-project/pull/106681
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>From 88cbdf9765e42dee7d2b050dcf8a20a08b4b148f Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/7] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert commented:
LGTM
https://github.com/llvm/llvm-project/pull/109598
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KanRobert wrote:
> I suppose the name of relocation used by binutils is
> R_X86_64_CODE_4_GOTPCRELX Also binutils has added
> R_X86_64_CODE_5_GOTPCRELX/R_X86_64_CODE_6_GOTPCRELX, for evex relocation
> Refer to
> [bminor/binutils-gdb@3d5a60d](https://github.com/bminor/binutils-gdb/commit/3d5a6
https://github.com/KanRobert ready_for_review
https://github.com/llvm/llvm-project/pull/106681
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>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/7] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/6] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/5] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
KanRobert wrote:
TODO:
* [ ] Pass tests lld/test/ELF/x86-64-gotpc-relax.s and
lld/test/ELF/x86-64-gotpc-relax-nopic.s
https://github.com/llvm/llvm-project/pull/106681
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>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/4] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/3] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/2] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert converted_to_draft
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/KanRobert created
https://github.com/llvm/llvm-project/pull/106681
For
movname@GOTPCREL(%rip), %reg
test %reg, name@GOTPCREL(%rip)
binop name@GOTPCREL(%rip), %reg
where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructi
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/104781
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https://github.com/KanRobert approved this pull request.
MC and foldtable change LGTM
https://github.com/llvm/llvm-project/pull/101600
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https://github.com/KanRobert approved this pull request.
LGTM, but please put the link for the discussion in GCC community in description
https://github.com/llvm/llvm-project/pull/103898
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https://github.com/KanRobert commented:
LGTM for the fold table change
https://github.com/llvm/llvm-project/pull/101599
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LGTM
https://github.com/llvm/llvm-project/pull/101783
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https://github.com/KanRobert commented:
LGTM
https://github.com/llvm/llvm-project/pull/101598
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@@ -785,9 +785,9 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
raw_ostream &o2,
break;
}
- // We assume that the index can fit into uint16_t.
- assert(sEntryNumber < 65536U &&
- "Index into ModRMDecision is too large for uint16_t!");
+ // We
@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
KanRobert wrote:
Is this fail related to your PR?
```
LLVM-Unit :: tools/llvm-cfi-verify/./CFIVerifyTests/2/49
```
https://github.com/llvm/llvm-project/pull/101616
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@@ -214,6 +214,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_W_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX_W);
+else {
+ errs() << "Instruction does not
@@ -223,6 +227,10 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB_U(IC_EVEX_XD);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB_U(IC_EVEX);
+else {
+ errs() << "Instruction does not use
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/101452
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@@ -1219,6 +1219,9 @@ static int getInstructionID(struct InternalInstruction
*insn,
attrMask |= ATTR_EVEXKZ;
if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXB;
+ if (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) &&
--
@@ -575,6 +575,31 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_EVEX_W_NF:
case IC_EVEX_W_B_NF:
return false;
+ case IC_EVEX_B_U:
+ case IC_EVEX_XS_B_U:
+ case IC_EVEX_XD_B_U:
+ case IC_EVEX_OPSIZE_B_U:
+ case IC_EVEX_W_B_U:
+ case IC_EVEX_W
@@ -1219,6 +1219,9 @@ static int getInstructionID(struct InternalInstruction
*insn,
attrMask |= ATTR_EVEXKZ;
if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXB;
+ if (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) &&
+
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
@@ -575,6 +575,31 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_EVEX_W_NF:
case IC_EVEX_W_B_NF:
return false;
+ case IC_EVEX_B_U:
+ case IC_EVEX_XS_B_U:
+ case IC_EVEX_XD_B_U:
+ case IC_EVEX_OPSIZE_B_U:
+ case IC_EVEX_W_B_U:
+ case IC_EVEX_W
@@ -926,7 +951,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o,
unsigned &i) const {
else
o << "IC_VEX";
- if ((index & ATTR_EVEX) && (index & ATTR_EVEXL2))
+ if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU))
+; // Ignore ATTR_VEX
@@ -131,7 +131,7 @@ class X86OpcodePrefixHelper {
// | RM (VR) | EVEX_X | EVEX_B | modrm.r/m | VR | Dest or Src |
// | RM (GPR) | EVEX_B' | EVEX_B | modrm.r/m | GPR | Dest or Src |
// | BASE | EVEX_B' | EVEX_B | modrm.r/m | GPR | MA |
- //
@@ -111,9 +111,9 @@ class X86OpcodePrefixHelper {
// 0b11: F2
// EVEX (4 bytes)
- // +-+ +---+ ++
++
- // | 62h | | RXBR' | B'mmm | | W | | X' | pp | | z | L'L | b | v' | aaa
|
- // +-+ +---
Author: Shengchen Kan
Date: 2024-07-31T11:03:23+08:00
New Revision: 57acabb8e09baa38b156965b2dc567a8c7eb2429
URL:
https://github.com/llvm/llvm-project/commit/57acabb8e09baa38b156965b2dc567a8c7eb2429
DIFF:
https://github.com/llvm/llvm-project/commit/57acabb8e09baa38b156965b2dc567a8c7eb2429.diff
https://github.com/KanRobert closed
https://github.com/llvm/llvm-project/pull/101151
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>From 650f29dd40714ebe52bf5d0a407bd45b9d248269 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 30 Jul 2024 16:26:39 +0800
Subject: [PATCH 1/5] [Driver,CodeGen] Report error when enabling 64-bit-only
f
@@ -309,8 +309,8 @@
// HRESET: "-target-feature" "+hreset"
// NO-HRESET: "-target-feature" "-hreset"
-// RUN: %clang --target=i386 -march=i386 -muintr %s -### 2>&1 | FileCheck
-check-prefix=UINTR %s
-// RUN: %clang --target=i386 -march=i386 -mno-uintr %s -### 2>&1 | FileCheck
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/101151
>From 650f29dd40714ebe52bf5d0a407bd45b9d248269 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 30 Jul 2024 16:26:39 +0800
Subject: [PATCH 1/4] [Driver,CodeGen] Report error when enabling 64-bit-only
f
@@ -266,13 +270,24 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
}
bool IsNegative = Name.starts_with("no-");
+
+bool Not64Bit = ArchType != llvm::Triple::x86_64;
KanRobert wrote:
It would not. We check the option
@@ -248,6 +248,10 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name));
}
+ llvm::StringSet<> SubFeaturesOfAPX = {"egpr", "push2pop2", "ppx", "ndd",
+
@@ -309,8 +309,8 @@
// HRESET: "-target-feature" "+hreset"
// NO-HRESET: "-target-feature" "-hreset"
-// RUN: %clang --target=i386 -march=i386 -muintr %s -### 2>&1 | FileCheck
-check-prefix=UINTR %s
-// RUN: %clang --target=i386 -march=i386 -mno-uintr %s -### 2>&1 | FileCheck
https://github.com/KanRobert commented:
Update the tests for `m512_maskz_cvt_roundepu64_ps` e.t.c (in
avx512dq-builtins.c )?
https://github.com/llvm/llvm-project/pull/99691
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Author: Shengchen Kan
Date: 2024-07-19T12:34:41+08:00
New Revision: 88e9bd822fe088eff74f49081b890071538fa40c
URL:
https://github.com/llvm/llvm-project/commit/88e9bd822fe088eff74f49081b890071538fa40c
DIFF:
https://github.com/llvm/llvm-project/commit/88e9bd822fe088eff74f49081b890071538fa40c.diff
@@ -175,8 +175,6 @@ X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",
34)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect", 35)
// Below Features has some missings comparing to gcc, it's because gcc has some
// not one-to-one mapped in llvm.
-X86_FEATURE_
Author: Shengchen Kan
Date: 2024-07-16T10:59:12+08:00
New Revision: d82c75ebc0483971b768dd5ff077789262ffd9c0
URL:
https://github.com/llvm/llvm-project/commit/d82c75ebc0483971b768dd5ff077789262ffd9c0
DIFF:
https://github.com/llvm/llvm-project/commit/d82c75ebc0483971b768dd5ff077789262ffd9c0.diff
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@@ -2711,6 +2711,8 @@ static void CollectArgsForIntegratedAssembler(Compilation
&C,
}
if (!UseRelaxRelocations)
CmdArgs.push_back("-mrelax-relocations=no");
+ if (Args.hasArg(options::OPT_msse2avx))
+CmdArgs.push_back("-msse2avx");
KanRobert wrote
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/96860
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@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -140,6 +141,10 @@
llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
cl::init(true));
MCBINDOPT(X86RelaxRelocations);
+ static cl::opt X86Sse2Avx(
+ "x86-sse2avx", cl::desc("Convert SSE Instructions to AVX Instructions"));
--
@@ -8367,6 +8369,9 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
+ if (Args.hasArg(options::OPT_msse2avx))
+Args.AddLastArg(CmdArgs, options::OPT_msse2avx
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
Martin =?utf-8?q?Storsj=C3=B6?=
Message-ID:
In-Reply-To:
https://github.com/KanRobert commented:
LGTM
https://github.com/llvm/llvm-project/pull/98478
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@@ -335,6 +337,31 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
}
+void X86InstrMappingEmitter::emitSSE2AVXTable(
+ArrayRef Insts, raw_ostream &OS) {
+ std::vector Table;
+ for (const CodeGenInst
KanRobert wrote:
Hmm, what's your usage?
#define A
before
#include
?
https://github.com/llvm/llvm-project/pull/98478
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@@ -5201,6 +5201,10 @@ def mrelax_all : Flag<["-"], "mrelax-all">,
Group,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
HelpText<"(integrated-as) Relax all machine instructions">,
MarshallingInfoFlag>;
+def msse2avx : Flag<["-"], "msse2avx">, Group,
+ Visibility<[C
@@ -335,6 +337,31 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
}
+void X86InstrMappingEmitter::emitSSE2AVXTable(
+ArrayRef Insts, raw_ostream &OS) {
+ std::vector Table;
+ for (const CodeGenInst
KanRobert wrote:
Add -att suffix
https://github.com/llvm/llvm-project/pull/96860
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@@ -0,0 +1,89 @@
+# RUN: %clang -march=x86-64 -msse2avx %s -c -o %t
KanRobert wrote:
Do not add end2end test. Check test for other flags.
https://github.com/llvm/llvm-project/pull/96860
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KanRobert wrote:
> How easy would it be to add an option for this to update inline asm? I'm not
> asking you to do this here, I just want to know if this approach would make
> it straightforward to add in the future.
Should we touch the inline asm? (GCC doesn't https://godbolt.org/z/o9MM9br95
KanRobert wrote:
Don't add clang test in MC folder. You can add front-end tests to check the
flag is passed down correctly.
https://github.com/llvm/llvm-project/pull/96860
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@@ -4761,6 +4761,7 @@ def mno_tls_direct_seg_refs : Flag<["-"],
"mno-tls-direct-seg-refs">, Group,
MarshallingInfoFlag>;
def mno_relax_all : Flag<["-"], "mno-relax-all">, Group;
+def mno_sse2avx : Flag<["-"], "mno-sse2avx">, Group;
KanRobert wrote:
I wonder
@@ -8359,6 +8359,9 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
+ if (Args.hasFlag(options::OPT_msse2avx, options::OPT_mno_sse2avx, true))
+Args.addOptIn
@@ -5186,6 +5187,10 @@ def mrelax_all : Flag<["-"], "mrelax-all">,
Group,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
HelpText<"(integrated-as) Relax all machine instructions">,
MarshallingInfoFlag>;
+def msse2avx : Flag<["-"], "msse2avx">, Group,
@@ -5186,6 +5187,10 @@ def mrelax_all : Flag<["-"], "mrelax-all">,
Group,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
HelpText<"(integrated-as) Relax all machine instructions">,
MarshallingInfoFlag>;
+def msse2avx : Flag<["-"], "msse2avx">, Group,
@@ -8359,6 +8359,9 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
+ if (Args.hasFlag(options::OPT_msse2avx, options::OPT_mno_sse2avx, true))
+Args.addOptIn
https://github.com/KanRobert closed
https://github.com/llvm/llvm-project/pull/97721
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/97721
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https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/97721
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KanRobert wrote:
Updated.
https://github.com/llvm/llvm-project/pull/97721
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https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/97721
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KanRobert wrote:
This test is too verbose, not robust and miss coverage. I would suggest the
following
```
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64 -mattr=+branch-hint
@@ -54,6 +55,14 @@
using namespace llvm;
+static cl::opt EnableBranchHint("branch-hint",
KanRobert wrote:
`enable-branch-hint` is more in line with our current naming habits
https://github.com/llvm/llvm-project/pull/97721
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@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
KanRobert wrote:
Drop -show-mc-encoding
ht
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition bra
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition bra
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition bra
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition bra
@@ -749,6 +749,11 @@ def TuningUseGLMDivSqrtCosts
: SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
"Use Goldmont specific floating point div/sqrt costs">;
+// Starting with Redwood Cove architecture, the branch has branch taken hint
+// (i
@@ -749,6 +749,11 @@ def TuningUseGLMDivSqrtCosts
: SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
"Use Goldmont specific floating point div/sqrt costs">;
+// Starting with Redwood Cove architecture, the branch has branch taken hint
+// (i
https://github.com/KanRobert closed
https://github.com/llvm/llvm-project/pull/97525
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