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@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
@@ -3178,98 +3178,74 @@ bool
SPIRVInstructionSelector::selectFirstBitSet64Overflow(
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const {
+ // SPIR-V only allow vecs of size 2,3,4. Calling w
spall wrote:
Waiting on #120630
https://github.com/llvm/llvm-project/pull/119820
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spall wrote:
> This looks correct, but how much work is it to update all of these tests to
> have fast math enabled rather than explicitly disabling it? I worry that (1)
> folks looking at these tests in the future will think that disabling fast
> math is a meaningful part of the test and (2)
https://github.com/spall closed https://github.com/llvm/llvm-project/pull/117245
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@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/116858
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@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
https://github.com/spall approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/117245
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@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/119820
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https://github.com/llvm/llvm-project/pull/119820
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https://github.com/spall created
https://github.com/llvm/llvm-project/pull/119820
Make fast math the default for HLSL
Closes #108597
>From d167cd92875f7aec8ed3ab15c3321ee9000e8481 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Thu, 12 Dec 2024 20:35:47 +
Subject: [PATCH 1/2] make fast m
spall wrote:
I'd also update your description to mention fixing the vector > size 2 bug in
FirstBitHigh as well, by making this code general purpose for both firstbitlow
and firstbithigh.
https://github.com/llvm/llvm-project/pull/116858
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@@ -96,15 +96,20 @@ class SPIRVInstructionSelector : public InstructionSelector
{
bool selectFirstBitHigh(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I, bool IsSigned) const;
- bool selectFirstBitHigh16(Register ResVReg, const SPIRVT
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
@@ -3166,109 +3171,228 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
-const SPIRVTyp
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/118842
>From 2e932a57ccb992b856b58bec4c30c6b64f24f711 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Thu, 28 Nov 2024 16:23:57 +
Subject: [PATCH 1/5] Flat casts WIP
---
clang/include/clang/AST/OperationKinds.def
spall wrote:
Work for this PR begins at 'splat cast wip' commit.
https://github.com/llvm/llvm-project/pull/118992
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https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/118992
>From 2e932a57ccb992b856b58bec4c30c6b64f24f711 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Thu, 28 Nov 2024 16:23:57 +
Subject: [PATCH 1/8] Flat casts WIP
---
clang/include/clang/AST/OperationKinds.def
https://github.com/spall created
https://github.com/llvm/llvm-project/pull/118992
Implement HLSL Flat casting that handles splatting for arrays and structs, and
vectors if splatting from a vec1.
Closes #100609 and Closes #100619
Depends on #118842
>From 2e932a57ccb992b856b58bec4c30c6b64f24f7
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/118842
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https://github.com/spall created
https://github.com/llvm/llvm-project/pull/118842
Implement HLSL Flat casting excluding splat cases
Partly closes #100609 and #100619
>From 2e932a57ccb992b856b58bec4c30c6b64f24f711 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Thu, 28 Nov 2024 16:23:57 +
spall wrote:
I'm going to change the name of the Cast to HLSLFlatCast.
https://github.com/llvm/llvm-project/pull/118842
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https://github.com/llvm/llvm-project/pull/111047
>From 119def060924f13bd1fe07f6d73ce27a1b52ea12 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Tue, 17 Sep 2024 20:25:46 +
Subject: [PATCH 1/8] theoretically fix issue
---
clang/lib/Sema/SemaType.cpp | 4 ++
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111047
>From 119def060924f13bd1fe07f6d73ce27a1b52ea12 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Tue, 17 Sep 2024 20:25:46 +
Subject: [PATCH 1/8] theoretically fix issue
---
clang/lib/Sema/SemaType.cpp | 4 ++
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -3158,6 +3172,166 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
}
}
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+ const SPIRVType *ResType,
+
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111047
>From 119def060924f13bd1fe07f6d73ce27a1b52ea12 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Tue, 17 Sep 2024 20:25:46 +
Subject: [PATCH 1/7] theoretically fix issue
---
clang/lib/Sema/SemaType.cpp | 4 ++
https://github.com/spall approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/114847
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https://github.com/spall approved this pull request.
https://github.com/llvm/llvm-project/pull/113382
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@@ -1762,6 +1765,37 @@ bool SPIRVInstructionSelector::selectSign(Register
ResVReg,
return Result;
}
+bool SPIRVInstructionSelector::selectWaveActiveCountBits(
+Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
+ assert(I.getNumOperands() == 3);
+ as
https://github.com/spall closed https://github.com/llvm/llvm-project/pull/111082
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spall wrote:
Waiting on #114482
https://github.com/llvm/llvm-project/pull/111082
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@@ -85,6 +85,8 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
https://github.com/spall deleted
https://github.com/llvm/llvm-project/pull/112400
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@@ -85,6 +85,8 @@ def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLV
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0
@@ -4690,8 +4690,9 @@ void CodeGenFunction::EmitCallArg(CallArgList &args,
const Expr *E,
return emitWritebackArg(*this, args, CRE);
}
- assert(type->isReferenceType() == E->isGLValue() &&
- "reference binding to unmaterialized r-value!");
+ assert(type->isArr
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/111082
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@@ -449,6 +449,15 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
return Res;
}
+Register SPIRVGlobalRegistry::getOrCreateConstScalarOrVector(
+uint64_t Val, MachineInstr &I, SPIRVType *SpvType,
+const SPIRVInstrInfo &TII, bool ZeroAsNull) {
+ if (SpvTy
@@ -2717,82 +2717,82 @@ bool
SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
Register FBHReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
Result &= selectFirstBitHigh32(FBHReg, postCastT, I, bitcastReg, IsSigned);
- // 3. check if result of e
@@ -37,13 +39,12 @@ define noundef i32 @firstbituhigh_i64(i64 noundef %a) {
entry:
; CHECK: [[O:%.*]] = OpBitcast %[[#]] %[[#]]
; CHECK: [[N:%.*]] = OpExtInst %[[#]] %[[#]] FindUMsb [[O]]
-; CHECK: [[M:%.*]] = OpVectorShuffle %[[#]] [[N]] [[N]] 0
-; CHECK: [[L:%.*]] = OpVectorS
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111047
>From 0797f19cad4ca9cf605725de1ac838cccacda1fc Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Tue, 17 Sep 2024 20:25:46 +
Subject: [PATCH 1/6] theoretically fix issue
---
clang/lib/Sema/SemaType.cpp | 4 ++
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111047
>From 0797f19cad4ca9cf605725de1ac838cccacda1fc Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Tue, 17 Sep 2024 20:25:46 +
Subject: [PATCH 1/6] theoretically fix issue
---
clang/lib/Sema/SemaType.cpp | 4 ++
https://github.com/spall closed https://github.com/llvm/llvm-project/pull/113189
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https://github.com/llvm/llvm-project/pull/113189
>From 23d62026c8338e6ad92495cfcaa54ff1fa5d08f0 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Wed, 16 Oct 2024 19:00:08 +
Subject: [PATCH 1/5] implement countbits correctly
---
clang/lib/Headers/hlsl/hlsl_
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/113189
>From 12cac48dcc10ef9c5fccba2c22911f420298b98b Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Wed, 16 Oct 2024 19:00:08 +
Subject: [PATCH 1/4] implement countbits correctly
---
clang/lib/Headers/hlsl/hlsl_
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111082
>From 6239941c302f616f87ed652151e828a8eae1054c Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Mon, 23 Sep 2024 22:10:59 +
Subject: [PATCH 1/8] implement firstbithigh hlsl builtin
---
clang/include/clang/Ba
@@ -0,0 +1,107 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK: OpMemoryModel Logical GLSL450
+
+define noundef i32 @f
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/111082
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>From 6239941c302f616f87ed652151e828a8eae1054c Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Mon, 23 Sep 2024 22:10:59 +
Subject: [PATCH 1/7] implement firstbithigh hlsl builtin
---
clang/include/clang/Ba
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/113189
>From 12cac48dcc10ef9c5fccba2c22911f420298b98b Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Wed, 16 Oct 2024 19:00:08 +
Subject: [PATCH 1/3] implement countbits correctly
---
clang/lib/Headers/hlsl/hlsl_
@@ -2626,6 +2671,148 @@ Register
SPIRVInstructionSelector::buildPointerToResource(
MIRBuilder);
}
+bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
+const
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/111082
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@@ -424,7 +424,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
LLT LLTy = LLT::scalar(64);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
-CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
+
@@ -461,6 +461,67 @@ class OpLowerer {
});
}
+ [[nodiscard]] bool lowerCtpopToCBits(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int32Ty = IRB.getInt32Ty();
+
+return replaceFunction(F, [&](CallInst *CI) -> Error {
+ IRB.SetInsertPoint(
@@ -808,6 +835,20 @@ bool SPIRVInstructionSelector::selectExtInst(Register
ResVReg,
return false;
}
+bool SPIRVInstructionSelector::selectNAryOpWithSrcs(Register ResVReg,
+const SPIRVType *ResType,
+
@@ -424,7 +424,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
LLT LLTy = LLT::scalar(64);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
-CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
+
@@ -461,6 +461,67 @@ class OpLowerer {
});
}
+ [[nodiscard]] bool lowerCtpopToCBits(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int32Ty = IRB.getInt32Ty();
+
+return replaceFunction(F, [&](CallInst *CI) -> Error {
+ IRB.SetInsertPoint(
@@ -4690,8 +4690,9 @@ void CodeGenFunction::EmitCallArg(CallArgList &args,
const Expr *E,
return emitWritebackArg(*this, args, CRE);
}
- assert(type->isReferenceType() == E->isGLValue() &&
- "reference binding to unmaterialized r-value!");
+ assert(type->isArr
@@ -461,6 +461,67 @@ class OpLowerer {
});
}
+ [[nodiscard]] bool lowerCtpopToCBits(Function &F) {
+IRBuilder<> &IRB = OpBuilder.getIRB();
+Type *Int32Ty = IRB.getInt32Ty();
+
+return replaceFunction(F, [&](CallInst *CI) -> Error {
+ IRB.SetInsertPoint(
@@ -705,66 +705,74 @@ float4 cosh(float4);
#ifdef __HLSL_ENABLE_16_BIT
_HLSL_AVAILABILITY(shadermodel, 6.2)
-_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount)
-int16_t countbits(int16_t);
spall wrote:
When I asked Justin about this he pointed to this link:
spall wrote:
> > > Despite all of this, DXC does indeed support 16- and 64-bit overloads, as
> > > seen here: https://hlsl.godbolt.org/z/qbc17xz35
> > > Note that the return type of the operation is not overloaded - all of the
> > > overloads of this function return uint.
> >
> >
> > Why is t
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/113189
>From f110f3167769d91dd87b260b30c2a61cc754b619 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Wed, 16 Oct 2024 19:00:08 +
Subject: [PATCH 1/2] implement countbits correctly
---
clang/lib/Headers/hlsl/hlsl_
https://github.com/spall created
https://github.com/llvm/llvm-project/pull/113189
Restricts hlsl countbits to always return a uint32.
Implements a lowering from llvm.ctpop which has an overloaded return type to
dxil cbits op which always returns uint32.
Closes #112779
>From f110f3167769d91dd8
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111082
>From 62af64102d96405d9a572a054ad4c2fa87ba8867 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Mon, 23 Sep 2024 22:10:59 +
Subject: [PATCH 1/6] implement firstbithigh hlsl builtin
---
clang/include/clang/Ba
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111082
>From 62af64102d96405d9a572a054ad4c2fa87ba8867 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Mon, 23 Sep 2024 22:10:59 +
Subject: [PATCH 1/5] implement firstbithigh hlsl builtin
---
clang/include/clang/Ba
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111082
>From 62af64102d96405d9a572a054ad4c2fa87ba8867 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Mon, 23 Sep 2024 22:10:59 +
Subject: [PATCH 1/4] implement firstbithigh hlsl builtin
---
clang/include/clang/Ba
https://github.com/spall approved this pull request.
https://github.com/llvm/llvm-project/pull/108396
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spall wrote:
> It is not correct to limit firstbithigh to 32 bit integers. There are a
> couple of reasons that might make one think that it is, but we do in fact
> want/need to support int16 and int64 here.
>
> 1. The [HLSL
> docs](https://learn.microsoft.com/en-us/windows/win32/direct3d
spall wrote:
> It is not correct to limit firstbithigh to 32 bit integers. There are a
> couple of reasons that might make one think that it is, but we do in fact
> want/need to support int16 and int64 here.
>
> 1. The [HLSL
> docs](https://learn.microsoft.com/en-us/windows/win32/direct3d
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111082
>From e9ed9f9a0415544781f8334b305eb3916fc0862c Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Mon, 23 Sep 2024 22:10:59 +
Subject: [PATCH 1/4] implement firstbithigh hlsl builtin
---
clang/include/clang/Ba
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/111209
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@@ -1643,6 +1646,23 @@ bool SPIRVInstructionSelector::selectLength(Register
ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectDegrees(Register ResVReg,
+ const SPIRVType *ResType,
+
@@ -2625,6 +2645,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
return selectFmix(ResVReg, ResType, I);
case Intrinsic::spv_length:
return selectLength(ResVReg, ResType, I);
+ case Intrinsic::spv_degrees:
+return selectDegrees(ResVReg, Res
https://github.com/spall edited https://github.com/llvm/llvm-project/pull/111082
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@@ -0,0 +1,37 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK: OpMemoryModel Logical GLSL450
+
+define noundef i32 @fi
https://github.com/spall approved this pull request.
LGTM but I didn't look too closely at the tests.
https://github.com/llvm/llvm-project/pull/110802
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@@ -0,0 +1,37 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
spall wrote:
I removed the non-32 bit tests, exce
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111082
>From e9ed9f9a0415544781f8334b305eb3916fc0862c Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Mon, 23 Sep 2024 22:10:59 +
Subject: [PATCH 1/3] implement firstbithigh hlsl builtin
---
clang/include/clang/Ba
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111082
>From e9ed9f9a0415544781f8334b305eb3916fc0862c Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Mon, 23 Sep 2024 22:10:59 +
Subject: [PATCH 1/2] implement firstbithigh hlsl builtin
---
clang/include/clang/Ba
https://github.com/spall created
https://github.com/llvm/llvm-project/pull/111082
Implements elementwise firstbithigh hlsl builtin.
Implements firstbituhigh intrinsic for spirv and directx, which handles
unsigned integers
Implements firstbitshigh intrinsic for spirv and directx, which handles s
https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/111047
>From c73ce3707e59242b8ccbb6757a290938c2d39e5e Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Tue, 17 Sep 2024 20:25:46 +
Subject: [PATCH 1/5] theoretically fix issue
---
clang/lib/Sema/SemaType.cpp | 4 ++
https://github.com/spall created
https://github.com/llvm/llvm-project/pull/111047
Get inout/out parameters working for HLSL Arrays.
Utilizes the fix from #109323, and corrects the assignment behavior slightly to
allow for Non-LValues on the RHS.
Closes #106917
>From c73ce3707e59242b8ccbb6757
https://github.com/spall closed https://github.com/llvm/llvm-project/pull/109323
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https://github.com/spall updated
https://github.com/llvm/llvm-project/pull/109323
>From f4d72ce6faca5498f184069b7c5d22841a449e74 Mon Sep 17 00:00:00 2001
From: Sarah Spall
Date: Wed, 18 Sep 2024 22:19:07 +
Subject: [PATCH 1/3] enable array by value assignment
---
clang/include/clang/AST/C
https://github.com/spall approved this pull request.
Code LGTM; didn't look at the tests too closely.
https://github.com/llvm/llvm-project/pull/110187
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https://github.com/spall approved this pull request.
https://github.com/llvm/llvm-project/pull/108849
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