lenary wrote:
Please can you undo these whitespace changes, given you're not really making
changes to this file
https://github.com/llvm/llvm-project/pull/121394
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@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals :
SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
+
+def FeatureVendorMIPSCMove
https://github.com/lenary commented:
Some small notes, the one about using RISCVExtension will probably have the
most knock-on work (run both the llvm and the clang test suites after that
change, to see where that info gets to)
https://github.com/llvm/llvm-project/pull/121394
_
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https://github.com/llvm/llvm-project/pull/121394
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https://github.com/lenary approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/122256
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@@ -313,6 +313,7 @@ enum OperandType : unsigned {
OPERAND_UIMM8_LSB000,
OPERAND_UIMM8_GE32,
OPERAND_UIMM9_LSB000,
+ OPERAND_UIMM10,
lenary wrote:
Please can you add `CASE_OPERAND_UIMM(10)` to the right place in
`RISCVInstrInfo::verifyInstruction`?
htt
https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/121752
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https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/110657
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https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/121292
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@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"]
@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia"
+let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in {
+
@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia"
+let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in {
+
https://github.com/lenary approved this pull request.
LGTM, but please wait for Craig to approve as well.
https://github.com/llvm/llvm-project/pull/119823
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https://github.com/llvm/llvm-project/pull/117612
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lenary wrote:
> > @rzinsly do you need someone to commit this?
>
> Yes, please.
Please turn off [Keep my email addresses
private](https://github.com/settings/emails) setting in your account. Otherwise
the commit will be from the github hidden email which we don't use in LLVM. See
[LLVM
Disc
https://github.com/lenary approved this pull request.
LGTM
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@@ -0,0 +1,87 @@
+//===-- xray_trampoline_riscv32.s --*- ASM
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,87 @@
+//===-- xray_trampoline_riscv32.s --*- ASM
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
https://github.com/lenary approved this pull request.
LGTM.
I note Craig has questions about the spec, we will ensure those are relayed to
the spec authors, but they don't relate to encoding/assembling problems, so I'm
not sure if they should block landing this.
https://github.com/llvm/llvm-p
https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/117987
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@@ -771,9 +772,11 @@ Error RISCVISAInfo::checkDependency() {
return getIncompatibleError("xwchc", "zcb");
}
- if (Exts.count("xqcicsr") != 0 && (XLen != 32)) {
-return getError("'xqcicsr' is only supported for 'rv32'");
- }
+ for (auto Ext : XqciExts)
+if (E
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@@ -22,6 +22,28 @@
// Instruction Class Templates
//===--===//
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+class QCILoad_ScaleIdx func4, string opcodestr>
+: RVInstRBase<0b111, OPC_CUSTOM_0,
https://github.com/lenary commented:
The encodings and functionality here are correct, but we're missing a test and
it would be good to add a comment to the scaled store tablegen class.
https://github.com/llvm/llvm-project/pull/117987
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@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,208 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v -O2 < %s \
+; RUN: | FileCheck %s -check-prefix=RV64I
lenary wrote:
Why is this only testing rv64?
https://github.com/ll
https://github.com/lenary approved this pull request.
I am out of the loop on the discussion in the call today, but I can confirm
this is a correct implementation of Xqcicsr, according to the specification.
https://github.com/llvm/llvm-project/pull/117169
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@@ -203,9 +203,28 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
// Atomic Extensions
+def FeatureStdExtZaamo
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
+def HasStdExtAOrZaamo
+: Predicate<"Subtarget->hasSt
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lenary wrote:
Kito and I have agreed `R` is a good way forwards for GPR pairs, and the
c-api-doc PR is approved (but not landed). I'll reword the description/message
to update our constraint choice when I land this, which I hope to get to later
today.
https://github.com/llvm/llvm-project/pul
lenary wrote:
I won't be merging this today. Instead, two changes/updates:
- Moving to use `R` instead of `Pr`, because kito pointed out that GCC cannot
use `P` for anything except immediate values (done as a fixup for the moment,
so we can back it out if we're struggling to agree on letters)
-
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From 0b98a56337d3210e82cac0f509eb7d3d547083f9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/3] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/116094
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https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/116094
>From 0b98a56337d3210e82cac0f509eb7d3d547083f9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/3] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/116094
This is a stacked PR. Just review 716b3d5055e95f161d8e0fc34c802a059266ffc1 (the
prior commit is #112983).
As suggested by @topperc, this tries to merge the two sets of register classes
created in #112983, GPRPa
@@ -74,7 +74,10 @@ def sub_gpr_odd : SubRegIndex<32, 32> {
}
} // Namespace = "RISCV"
-// Integer registers
+//===--===//
lenary wrote:
Landed as
https://github.com/llvm/llvm-project/commit
lenary wrote:
I'm not sure this requires re-review, so I plan to land this tomorrow (UK time)
if I don't hear anything else.
https://github.com/llvm/llvm-project/pull/112983
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lenary wrote:
The commit I just pushed up should be the final version, and not fundamentally
different from what was reviewed (but with various NFC patches split out).
I think I do have a route towards merging GPRPair and GPRF64Pair, but I'll do
that in a follow-up, as there's a mystery crash
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From 0b98a56337d3210e82cac0f509eb7d3d547083f9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds suppor
lenary wrote:
I will rewrite the description of the PR momentarily, once I've rebased over
the cleanup/comments to RISCVRegisterinfo.td
https://github.com/llvm/llvm-project/pull/112983
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@@ -952,14 +952,43 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, Res);
return;
}
+ case RISCVISD::BuildGPRPair: {
+SDValue Ops[] = {
+CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32),
+Node->getOperand(0),
+
@@ -21351,6 +21372,17 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
unsigned NumParts, MVT PartVT, std::optional CC) const {
bool IsABIRegCopy = CC.has_value();
EVT ValueVT = Val.getValueType();
+
+ if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From a63ead48585be1d6aa5e1b78926ede485e76e2f2 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/8] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From a63ead48585be1d6aa5e1b78926ede485e76e2f2 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/7] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
lenary wrote:
Two comments:
- I don't think the c-api-doc change is going to be accepted at this rate
- One of the nice things about the monorepo is that you can do a Clang+Backend
change like what this requires in a single PR, rather than committing it
bit-by-bit. Seeing the entire change in o
@@ -952,14 +952,43 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, Res);
return;
}
+ case RISCVISD::BuildGPRPair: {
+SDValue Ops[] = {
+CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32),
+Node->getOperand(0),
+
@@ -74,7 +74,10 @@ def sub_gpr_odd : SubRegIndex<32, 32> {
}
} // Namespace = "RISCV"
-// Integer registers
+//===--===//
lenary wrote:
I'll do my best to.
https://github.com/llvm/llvm-pro
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From a63ead48585be1d6aa5e1b78926ede485e76e2f2 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/5] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
lenary wrote:
> > Gentle Ping. I'm looking for answers to two questions:
> >
> > * [Should I] prepare a fixup commit that [uses `MVT::Untyped`] (and removes
> > the `riscv_*_pair` MVTs), if we think that's a better target-independent
> > approach?
>
> I guess so. I didn't know about the Syste
lenary wrote:
Sorry I didn't get to this over the weekend. LGTM.
https://github.com/llvm/llvm-project/pull/113942
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lenary wrote:
> > I think we shouldn't do this for RVA22, so as not to break existing users
> > of that profile, who may have a toolchain that doesn't support B.
> > This change makes sense to me for the RV*23 profiles, especially since your
> > change to RVM23 has been accepted.
>
> For RVA22
lenary wrote:
Gentle Ping. I'm looking for answers to two questions:
- [Should I] prepare a fixup commit that [uses `MVT::Untyped`] (and removes the
`riscv_*_pair` MVTs), if we think that's a better target-independent approach?
- Any advice on whether I should be digging deeply into changing
https://github.com/lenary edited
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https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/114524
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https://github.com/lenary approved this pull request.
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@@ -2238,6 +2256,17 @@ MVT
RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
return PartVT;
}
+unsigned
+RISCVTargetLowering::getNumRegisters(LLVMContext &Context, EVT VT,
lenary wrote:
This is to prevent an assert that is hit in
`R
lenary wrote:
I think we shouldn't do this for RVA22, so as not to break existing users of
that profile, who may have a toolchain that doesn't support B.
This change makes sense to me for the RV*23 profiles, especially since your
change to RVM23 has been accepted.
https://github.com/llvm/llvm
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https://github.com/lenary commented:
> Thanks! I just had a detailed look. Given that you have explained almost all
> the code detailedly, I think this PR looks great to me! Just some overall
> comments:
>
> 1. I personally like your proposal of adding new constraints, but we still
> need the
@@ -2224,6 +2231,17 @@ bool RISCVTargetLowering::isExtractSubvectorCheap(EVT
ResVT, EVT SrcVT,
return Index == 0 || Index == ResElts;
}
+EVT RISCVTargetLowering::getAsmOperandValueType(const DataLayout &DL, Type *Ty,
+bool All
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lenary wrote:
ping?
https://github.com/llvm/llvm-project/pull/112983
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lenary wrote:
> I haven't made it so if you enable all extensions that constitute Sha, Sha is
> implied.
Great! I think it's most clear if we have "extensions only require things they
are made up of" (i.e. all the implications/requirements point to earlier/lesser
extensions) and "profiles are
lenary wrote:
Today's changes address all the CI failures, by adding better checking before
turning BITCAST into `BuildPairF64` or `SplitF64` - the conditions are derived
from the conditions on `setOperationAction(ISD::BITCAST, MVT::i64, Custom)`
before this patch added more of the same.
htt
https://github.com/lenary approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/111668
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lenary wrote:
Sorry, got the rebase slightly wrong. Will re-do it tomorrow. Tests will likely
fail in the meantime. This only really affects the branch-relaxation tests.
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lenary wrote:
NVM about GlobalISel "Inline asm lowering is not supported for this target yet".
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lenary wrote:
I gave up on using `splitValueIntoRegisterParts` and
`joinRegisterPartsIntoValue`, and instead added a custom legalisation of
`BITCAST` with the 2*xlen type, which matches what we do for `BuildPairF64` and
`SplitF64`. This ended up being much more "symmetrical", which was nice.
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lenary wrote:
I think the first thing I might do tomorrow is some of the NFC cleanups and
commenting that is in this PR.
I'm not sure the register class renaming can happen quite yet.
https://github.com/llvm/llvm-project/pull/112983
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lenary wrote:
So, I've just pushed an update:
- This now adds the two new MVTs, as suggested by Craig. I'm a little concerned
if this causes a problem of using too much space in SelectionDAG tables. It's
definitely a concern.
- I'm using them from `getAsmOperandValueType`, which is the right pl
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@@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
let rs1 = 0;
let rs2 = 0b00010;
}
+
+def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
lenary wrote:
Nice, thanks!
https://github.com/llvm/llvm-project/pull/111668
__
@@ -129,6 +129,7 @@ on support follow.
``Smcdeleg`` Supported
``Smcsrind`` Supported
``Smepmp``Supported
+ ``Smrnmi``Supported
lenary wrote:
This should probably be "Assembly Support" - some of the other `*ret`
ins
lenary wrote:
> > The Arch64 MVT::i64x8 may be a way to work around this. We could have a
> > special pair MVT only used by inline assembly.
>
> Ok, this sounds doable - so something like `MVT::xlen_pair` is the way I'll
> lean, rather than a different type for rv32/rv64.
Turns out that MVTs
lenary wrote:
> I'm concerned that if we make i128 legal, we will have to write custom
> splitting code for every operation. Using v2i64 probably has other problems
> conflicting with the V extension fixed vector support.
I sort-of expected that making `i128` legal would be problematic, I did
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/112983
I wanted to push up this draft, to check that I was going a reasonable
direction with this work. It's still at an early stage.
I tried just adding the double-wide VTs to the GPRPair register class, but that
cau
lenary wrote:
Yeah, I went back and looked at that issue, it's helpful to know that it was
more than just the register allocator, that it was also copy propagation, which
wasn't obvious from the comments.
The failing tests are not related, but presumably caused by the rebase, but
I'll still
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112563
>From bbf0b885dc5912d4dc29abcec5fe7cee7cfd1758 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Wed, 16 Oct 2024 05:04:45 -0700
Subject: [PATCH 1/2] [RISCV] Inline Assembly: RVC constraint and N modifier
This ch
lenary wrote:
It would be great to get more comments than just Craig, so I can be sure that
there's wider consensus that adding this is good.
https://github.com/llvm/llvm-project/pull/112561
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lenary wrote:
I spent some time trying to write a test that should fail before, but doesn't
after, but it doesn't happen - I presume because x0 is reasonably dealt with by
the allocator. This maybe suggests the patch isn't needed? I'm not sure why we
do this for GPRs then.
https://github.com/
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112561
>From bbf0b885dc5912d4dc29abcec5fe7cee7cfd1758 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Wed, 16 Oct 2024 05:04:45 -0700
Subject: [PATCH] [RISCV] Inline Assembly: RVC constraint and N modifier
This change
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112563
>From bbf0b885dc5912d4dc29abcec5fe7cee7cfd1758 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Wed, 16 Oct 2024 05:04:45 -0700
Subject: [PATCH 1/2] [RISCV] Inline Assembly: RVC constraint and N modifier
This ch
lenary wrote:
(My approach with the test was to try to use all 32 GPRs, so have it fail when
it couldn't use x0 - doing so by marking ra, sp, gp, and tp as clobbered, and
passing 28 floats)
https://github.com/llvm/llvm-project/pull/112563
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@@ -348,6 +349,14 @@ bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr
*MI, unsigned OpNo,
if (!MO.isReg())
OS << 'i';
return false;
+case 'N': // Print the register encoding as an integer (0-31, or 0-7 when
lenary wrote:
Ah, ye
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/112563
I'm not sure if this fix is required, but I've written the patch anyway. This
does not cause test changes, but we haven't got tests that try to use all 32
registers in inline assembly.
Broadly, for GPRs, we mad
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/112561
This change implements support for the `cr` and `cf` register constraints
(which allocate a RVC GPR or RVC FPR respectively), and the `N` modifier (which
prints the raw encoding of a register rather than the nam
@@ -29,6 +29,14 @@ vint32m1_t test_vr(vint32m1_t a, vint32m1_t b) {
return ret;
}
+vint32m1_t test_vd(vint32m1_t a, vint32m1_t b) {
+// CHECK-LABEL: define{{.*}} @test_vd
+// CHECK: %0 = tail call asm sideeffect "vadd.vv $0, $1,
$2", "=^vd,^vd,^vd"( %a, %b)
+ vint32m1_t
https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/111653
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@@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
let rs1 = 0;
let rs2 = 0b00010;
}
+
+def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
lenary wrote:
Does this need a `Requires=[HasStdExtSmrnmi]` (And a definition of
`HasStdExtSmrnmi`)
@@ -0,0 +1,441 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --check-globals all --include-generated-funcs --version 4
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm -o
- %s | FileCheck %s
+
+__attribute_
https://github.com/lenary approved this pull request.
Nice catch in the test. Code still LGTM.
https://github.com/llvm/llvm-project/pull/108131
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