[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/120712 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)

@@ -0,0 +1,494 @@ +//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtWFusion, TuneShiftedZExtWFusion]>; +def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtWFusion, TuneShiftedZExtWFusion]>; +def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

wangpc-pp wrote: > > I thought the P550 was supposed to support RV64GCB, but that would require > > Zbs support, which isn't listed here. > > The P550 version in the HiFive Premier board does not support Zbs. ISA string > from /proc/cpuinfo is `rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf` Tha

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/122164 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs builtins (PR #96283)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/96283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs builtins (PR #96283)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/96283 >From 4b597ebf69de59d62e5587a27cedf2b12e831763 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Fri, 21 Jun 2024 16:09:13 +0800 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs builtins (PR #96283)

wangpc-pp wrote: Ping for comments. :-) https://github.com/llvm/llvm-project/pull/96283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs builtins (PR #96283)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/96283 >From 4b597ebf69de59d62e5587a27cedf2b12e831763 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Fri, 21 Jun 2024 16:09:13 +0800 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?= =

[clang] [llvm] [RISCV] Add support of Sdext, Sdtrig extentions (PR #120936)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/120936 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Remove unneeded RISCV tuple code (PR #121024)

https://github.com/wangpc-pp approved this pull request. LGTM. Nice cleanup. https://github.com/llvm/llvm-project/pull/121024 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support of Sdext, Sdtrig extentions (PR #120936)

@@ -842,6 +842,12 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">, AssemblerPredicate<(all_of FeatureStdExtH), "'H' (Hypervisor)">; +// Debugger extensions wangpc-pp wrote: They are also `Superviso

[clang] [llvm] [NFC] [RISCV] Refactor class RISCVExtension (PR #120040)

https://github.com/wangpc-pp approved this pull request. LGTM. Nice refactor! https://github.com/llvm/llvm-project/pull/120040 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NFC] [RISCV] Refactor class RISCVExtension (PR #120040)

@@ -22,11 +24,21 @@ // uses the record name by replacing Feature with Has. // value - Value to assign to the field in RISCVSubtarget when this // extension is enabled. Usually "true", but can be changed. -class RISCVExtension implies = [],

[clang] [llvm] [NFC] [RISCV] Refactor class RISCVExtension (PR #120040)

@@ -12,21 +12,32 @@ // Subclass of SubtargetFeature to be used when the feature is also a RISC-V // extension. Extensions have a version and may be experimental. +// NOTE: The extension name must start with +// - "FeatureStdExt" for standard extensions +// - "Featu

[clang] [llvm] [NFC] [RISCV] Refactor class RISCVExtension (PR #120040)

@@ -12,21 +12,32 @@ // Subclass of SubtargetFeature to be used when the feature is also a RISC-V // extension. Extensions have a version and may be experimental. +// NOTE: The extension name must start with +// - "FeatureStdExt" for standard extensions +// - "Featu

[clang] [llvm] [NFC] [RISCV] Refactor class RISCVExtension (PR #120040)

@@ -12,21 +12,32 @@ // Subclass of SubtargetFeature to be used when the feature is also a RISC-V // extension. Extensions have a version and may be experimental. +// NOTE: The extension name must start with +// - "FeatureStdExt" for standard extensions +// - "Featu

[clang] [llvm] [NFC] [RISCV] Refactor class RISCVExtension (PR #120040)

@@ -22,11 +22,20 @@ // uses the record name by replacing Feature with Has. // value - Value to assign to the field in RISCVSubtarget when this // extension is enabled. Usually "true", but can be changed. -class RISCVExtension implies = [],

[clang] [llvm] [NFC] [RISCV] Refactor class RISCVExtension (PR #120040)

@@ -22,11 +22,20 @@ // uses the record name by replacing Feature with Has. // value - Value to assign to the field in RISCVSubtarget when this // extension is enabled. Usually "true", but can be changed. -class RISCVExtension implies = [],

[clang] [llvm] [RISCV] Add MIPS P8700 processor (PR #119882)

@@ -1477,6 +1477,10 @@ def TuneConditionalCompressedMoveFusion def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; +def TuneMIPSP8700 +: SubtargetFeature<"m

[clang] [clang][RISCV] __riscv_v_intrinsic macro doesn't need zve32x (PR #117356)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/117356 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

wangpc-pp wrote: > Fails buildbot: > https://lab.llvm.org/buildbot/#/builders/24/builds/2791/steps/10/logs/stdio > > ``` > -- Testing: 83950 of 83951 tests, 48 workers -- > Testing: 0.. 10.. > FAIL: Clang :: Preprocessor/has_builtin_cpuid.c (15996 of 83950) > TEST 'Clang :

[clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/116231 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/116231 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

https://github.com/wangpc-pp commented: Add ReleaseNote to Clang? https://github.com/llvm/llvm-project/pull/116597 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

@@ -74,7 +74,10 @@ def sub_gpr_odd : SubRegIndex<32, 32> { } } // Namespace = "RISCV" -// Integer registers +//===--===// wangpc-pp wrote: Please land these comment/style changes first. htt

[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/112983 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

@@ -21351,6 +21372,17 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts( unsigned NumParts, MVT PartVT, std::optional CC) const { bool IsABIRegCopy = CC.has_value(); EVT ValueVT = Val.getValueType(); + + if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64

[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

https://github.com/wangpc-pp approved this pull request. Cheers! It seems using `untyped` saves some lines as well! LGTM with nits. https://github.com/llvm/llvm-project/pull/112983 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.l

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -104,6 +104,62 @@ // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalo

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/112983 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

@@ -2224,6 +2231,17 @@ bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, return Index == 0 || Index == ResElts; } +EVT RISCVTargetLowering::getAsmOperandValueType(const DataLayout &DL, Type *Ty, +bool All

[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

https://github.com/wangpc-pp commented: Thanks! I just had a detailed look. Given that you have explained almost all the code detailedly, I think this PR looks great to me! Just some overall comments: 1. I personally like your proposal of adding new constraints, but we still need the agreement

[clang] [llvm] [RISCV] Mark RVB23U64 and RVB23S64 as non-experimental (PR #113918)

https://github.com/wangpc-pp approved this pull request. Cheers! LGTM! https://github.com/llvm/llvm-project/pull/113918 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV]Add svvptc extension (PR #113882)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/113882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV]Add svvptc extension (PR #113758)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/113758 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV]Add svvptc extension (PR #113758)

https://github.com/wangpc-pp commented: Please update ReleaseNotes. https://github.com/llvm/llvm-project/pull/113758 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental (PR #113826)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/113826 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add the Sha extension (PR #113820)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/113820 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Use Sha extension in RVA23S64 profile (PR #113823)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/113823 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Supm extension to RVA23 profiles (PR #113619)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/113619 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Supm extension to RVA23 profiles (PR #113619)

https://github.com/wangpc-pp approved this pull request. LGTM. (And it's time to mask RV[A|B|M]23 as non-experimental now?) https://github.com/llvm/llvm-project/pull/113619 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[clang] [llvm] [RISCV] Mark pointer masking extensions as non-experimental (PR #113618)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/113618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Mark pointer masking extensions as non-experimental (PR #113618)

@@ -26,5 +26,5 @@ entry: ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) declare @llvm.masked.gather.nxv4i32.nxv4p0(, i32 immarg, , ) #1 -attributes #0 = { "target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve

[clang] [llvm] [RISCV] Mark pointer masking extensions as non-experimental (PR #113618)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/113618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Inline Assembly: RVC constraint and N modifier (PR #112561)

https://github.com/wangpc-pp approved this pull request. LGTM. I like this change and adding support of paired registers is on my todo list as well. https://github.com/llvm/llvm-project/pull/112561 ___ cfe-commits mailing list cfe-commits@lists.llvm.o

[clang] [llvm] [RISCV] Add Smrnmi extension (PR #111668)

@@ -276,6 +276,14 @@ foreach i = 0...15 in { foreach i = 0...63 in def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; +//===--===// +// Machine Non-Maskable Interrupt Handling +//===-

[clang] [llvm] Add Smrnmi extension (PR #111668)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/111668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add Smrnmi extension (PR #111668)

@@ -276,6 +276,14 @@ foreach i = 0...15 in { foreach i = 0...63 in def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; +//===--===// +// Machine Non-Maskable Interrupt Handling +//===-

[clang] [llvm] Add Smrnmi extension (PR #111668)

@@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; +def riscv_mnret

[clang] [clang][RISCV] Correct the SEW operand of indexed/fault only first segment intrinsics (PR #111476)

https://github.com/wangpc-pp approved this pull request. Make sense to me. It was wrong since when? https://github.com/llvm/llvm-project/pull/111476 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo

[clang] [clang][RISCV] Extend intrinsic size check variable from 16 -> 32 bits. NFC (PR #111481)

wangpc-pp wrote: > Why don’t any of our lit tests that use every intrinsic catch it? We don't see any error, is it because your downstream added some intrinsics? https://github.com/llvm/llvm-project/pull/111481 ___ cfe-commits mailing list cfe-commits

[clang] [clang][RISCV] Extend intrinsic size check variable from 16 -> 32 bits. NFC (PR #111481)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/111481 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Make the index of riscv_tuple_extract and riscv_tuple_insert be truncated rather than zero extended (PR #111466)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/111466 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Enable f16 vget/vset/vcreate/vlmul_ext/vlmul_trunc/vundefined intrinsics with Zvfhmin. (PR #109889)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/109889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Implement validateGlobalRegisterVariable. (PR #109596)

@@ -486,3 +486,15 @@ bool RISCVTargetInfo::validateCpuSupports(StringRef Feature) const { bool RISCVTargetInfo::isValidFeatureName(StringRef Name) const { return llvm::RISCVISAInfo::isSupportedExtensionFeature(Name); } + +bool RISCVTargetInfo::validateGlobalRegisterVariable(

[clang] [RISCV] Fix incorrect check prefix in riscv32-toolchain.c and riscv64-toolchain.c. NFC. (PR #109390)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/109390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/89051 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

wangpc-pp wrote: > What's the status of backend support for the large code model? That would > presumably be a prerequisite to landing this. It was just merged: https://github.com/llvm/llvm-project/pull/70308. https://github.com/llvm/llvm-project/pull/107817 ___

[clang] [clang] fix half && bfloat16 convert node expr codegen (PR #89051)

wangpc-pp wrote: > @JinjinLi868 are you still working on this? I can ask him. Is this PR blocking some of your works on float16/bf16? https://github.com/llvm/llvm-project/pull/89051 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists

[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

@@ -664,5 +664,9 @@ def FRM: RISCVReg<0, "frm">; // Shadow Stack register def SSP: RISCVReg<0, "ssp">; -// Dummy VCIX state register +// Dummy VCIX state register and its register class def VCIX_STATE : RISCVReg<0, "vcix_state">; +def : RISCVRegisterClass<[XLenVT], 32

[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/106359 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Remove `experimental` for vector crypto intrinsics (PR #106359)

https://github.com/wangpc-pp commented: Do we still need this? ``` def Experimental : SubtargetFeature<"experimental", "HasExperimental", "true", "Experimental intrinsics">; ``` https://github.com/llvm/llvm-project/pull/106359

[clang] [RISCV] Simplify reserse fixed regs (PR #104736)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/104736 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Simplify reserse fixed regs (PR #104736)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/104736 >From d45743a893a44dbb5da75d3dbe40dfbd34c14e71 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 19 Aug 2024 12:07:00 +0800 Subject: [PATCH 1/2] [RISCV] Simplify reserse fixed regs Add a macro to simpl

[clang] [RISCV] Simplify reserse fixed regs (PR #104736)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/104736 Add a macro to simplify some codes. >From d45743a893a44dbb5da75d3dbe40dfbd34c14e71 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 19 Aug 2024 12:07:00 +0800 Subject: [PATCH] [RISCV] Simplify resers

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/103709 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/103709 >From 0330ffdcd0ff0230ef8ba7fac5eff5874ba2e544 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Wed, 14 Aug 2024 15:14:36 +0800 Subject: [PATCH 1/2] [RISCV][MC] Support experimental extensions Zvbc32e and

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/103709 >From 0bdc302fb5b4dd7369d2f16a6da32412adbe7d7f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Wed, 14 Aug 2024 15:14:36 +0800 Subject: [PATCH 1/2] [RISCV][MC] Support experimental extensions Zvbc32e and

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -754,6 +754,17 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), "'Zvbc' (Vector Carryless Multiplication)">; +def FeatureStdExtZvbc32e +: RISCVExperimentalExtensio

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/103709 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/103709 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/102155 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

@@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `1.0 release specification `__. +``experimental

[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/103709 These two extensions add addtional instructions for carryless multiplication with 32-bits elements and Vector-Scalar GCM instructions. Please see https://github.com/riscv/riscv-isa-manual/pull/1306. >From 0b

[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith = SiFiveP400FEXQ0; defvar SiFiveP400F2I = SiFiveP400FEXQ0; def SiFiveP400FloatDiv: ProcResource<1>; +// Vector pipeline +def SiFiveP400VEXQ0: ProcResource<1>; wangpc-pp wrote: So there is 1 vec

[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith = SiFiveP400FEXQ0; defvar SiFiveP400F2I = SiFiveP400FEXQ0; def SiFiveP400FloatDiv: ProcResource<1>; +// Vector pipeline +def SiFiveP400VEXQ0: ProcResource<1>; wangpc-pp wrote: `EXQ0` means `exe

[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/102022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

@@ -304,6 +304,16 @@ // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs" // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck -check-prefix=MCPU-SIFIVE-P470 %s +// MCPU-SIFIVE-P470: "-target-cpu" "sifive-

[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

@@ -1371,7 +1371,6 @@ def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion() def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", "SiFive 7-Series processors">; - wangpc-pp wr

[clang] [RISCV][clang] Remove unused base type in `vfncvt` (PR #101646)

https://github.com/wangpc-pp approved this pull request. Make sense to me. (Do we have a way to test these generated builtins?) https://github.com/llvm/llvm-project/pull/101646 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.

[clang] [RISCV][NFC] Remove unneeded defining name of `vundefined` (PR #101643)

https://github.com/wangpc-pp commented: I don't think this will be better. We may keep these names so that these code can be self-explanatory. https://github.com/llvm/llvm-project/pull/101643 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[libunwind] [RISCV] Allow libunwind to build for rv32e (PR #98855)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/98855 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/101321 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

@@ -106,6 +106,7 @@ Changes to the RISC-V Backend * `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill the required alignment space with a sequence of `0x0` bytes (the requested fill value) rather than NOPs. +* Added Syntacore SCR4 CPUs: ``-mcpu=s

[clang] [NFC][clang] Fix typo of `riscv_rvv_vector_bits` in AttrDocs (PR #101046)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/101046 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/94352 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

@@ -290,8 +290,24 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList &Args, // 2. Get march (isa string) based on `-mcpu=` if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) { StringRef CPU = A->getValue(); -if (CPU == "native") +if (CPU == "nat

[clang] [llvm] [RISCV] Add QingKe "XW" compressed opcode extension (PR #97925)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/97925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental for bf16 extensions (PR #97996)

@@ -271,7 +271,7 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zalasr`` LLVM implements the `0.0.5 draft specification `__. -``experimental-zfbfmin``, ``experimental-zvfbfmin``

[clang] [libcxx] [llvm] [mlir] [openmp] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/97799 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [libcxx] [llvm] [mlir] [openmp] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/97799 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove SeenExtMap from RISCVISAInfo::parseArchString. (PR #97506)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/97506 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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