https://github.com/paulwalker-arm approved this pull request.
The documentation build failure has been verified locally as an existing
upstream issue and not the fault of this PR.
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@@ -237,6 +237,266 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVdN4v_log",
FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8), "_ZGV_LLVM_N8v")
+#elif defined(TLI
@@ -237,6 +237,266 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVdN4v_log",
FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8), "_ZGV_LLVM_N8v")
+#elif defined(TLI
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https://github.com/paulwalker-arm commented:
I could not spot any tests for the `<2 x float>` vector functions? Hopefully
it's as easy as adding extra RUN lines to veclib-function-calls.ll and
veclib-intrinsic-calls.ll. I'm thinking variants of LIBMVEC-NEON that use
`-force-vector-width=2`. I
@@ -237,6 +237,266 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVdN4v_log",
FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8), "_ZGV_LLVM_N8v")
+#elif defined(TLI
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@@ -1299,6 +1299,30 @@ static const VecDesc VecFuncs_LIBMVEC_X86[] = {
#undef TLI_DEFINE_LIBMVEC_X86_VECFUNCS
};
+static const VecDesc VecFuncs_LIBMVEC_AARCH64_VF2[] = {
+#define TLI_DEFINE_LIBMVEC_AARCH64_VF2_VECFUNCS
+#define TLI_DEFINE_VECFUNC(SCAL, VEC, VABI_PREFIX)
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@@ -1299,6 +1299,30 @@ static const VecDesc VecFuncs_LIBMVEC_X86[] = {
#undef TLI_DEFINE_LIBMVEC_X86_VECFUNCS
};
+static const VecDesc VecFuncs_LIBMVEC_AARCH64_VF2[] = {
+#define TLI_DEFINE_LIBMVEC_AARCH64_VF2_VECFUNCS
+#define TLI_DEFINE_VECFUNC(SCAL, VEC, VABI_PREFIX)
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@@ -1299,6 +1299,30 @@ static const VecDesc VecFuncs_LIBMVEC_X86[] = {
#undef TLI_DEFINE_LIBMVEC_X86_VECFUNCS
};
+static const VecDesc VecFuncs_LIBMVEC_AARCH64_VF2[] = {
+#define TLI_DEFINE_LIBMVEC_AARCH64_VF2_VECFUNCS
+#define TLI_DEFINE_VECFUNC(SCAL, VEC, VABI_PREFIX)
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@@ -177,16 +177,16 @@ define void @add_unique_ind32(ptr noalias nocapture %a,
i64 %n) {
; CHECK-LABEL: @add_unique_ind32(
; CHECK-NEXT: entry:
; CHECK-NEXT:[[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT:[[TMP1:%.*]] = shl i64 [[TMP0]], 2
+; CHECK-NEXT:[[
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>From e2642bec52f881c1d457f2c72ed3ae4ceec570e6 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 20 Mar 2025 14:58:51 +
Subject: [PATCH 1/3] Add SROA tests for casts between fixed and scalable
ty
@@ -4793,11 +4793,7 @@ Value
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
case SVE::BI__builtin_sve_svlen_u64: {
SVETypeFlags TF(Builtin->TypeModifier);
auto VTy = cast(getSVEType(TF));
paulwalker-arm wrote:
It turns out `getSVETy
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/142803
>From 0819cda292ccc0fa7376bb4c78d4884cf5845410 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Wed, 4 Jun 2025 13:06:31 +0100
Subject: [PATCH 1/2] [NFC][LLVM] Refactor
IRBuilder::Create{VScale,ElementCo
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/142803
CreateVScale took a scaling parameter that had a single use outside of
IRBuilder with all other callers having to create a redundant ConstantInt. To
work round this some code perferred to use CreateIntri
paulwalker-arm wrote:
ping
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https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/140591
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@@ -744,3 +744,38 @@
// CHECK-SMEB16B16: __ARM_FEATURE_SME2 1
// CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1
// CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1
+//
+// RUN: %clang --target=aarch64 -march=armv9-a+fp8 -x c -E -dM %s -o - |
FileCheck --check-prefix=CHECK-FP8 %s
+//
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https://github.com/paulwalker-arm commented:
Last question but otherwise this looks good to me.
https://github.com/llvm/llvm-project/pull/140591
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@@ -1046,6 +1082,29 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasSVEB16B16 = true;
HasSMEB16B16 = true;
}
+
+if (Feature == "+fp8")
+ HasFP8 = true;
+if (Feature == "+fp8fma")
+ HasFP8FMA = true;
+if (Feature =
@@ -1046,6 +1082,29 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasSVEB16B16 = true;
HasSMEB16B16 = true;
}
+
+if (Feature == "+fp8")
+ HasFP8 = true;
+if (Feature == "+fp8fma")
paulwalker-arm wrote:
`fp
@@ -744,3 +744,34 @@
// CHECK-SMEB16B16: __ARM_FEATURE_SME2 1
// CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1
// CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1
+//
+// RUN: %clang --target=aarch64 -march=armv9-a+fp8 -x c -E -dM %s -o - |
FileCheck --check-prefix=CHECK-FP8 %s
+//
@@ -1046,6 +1082,29 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasSVEB16B16 = true;
HasSMEB16B16 = true;
}
+
+if (Feature == "+fp8")
+ HasFP8 = true;
+if (Feature == "+fp8fma")
paulwalker-arm wrote:
I d
https://github.com/paulwalker-arm approved this pull request.
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@@ -744,3 +744,34 @@
// CHECK-SMEB16B16: __ARM_FEATURE_SME2 1
// CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1
// CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1
+//
+// RUN: %clang --target=aarch64 -march=armv9-a+fp8 -x c -E -dM %s -o - |
FileCheck --check-prefix=CHECK-FP8 %s
+//
@@ -5844,7 +5844,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Triple.getArch() != llvm::Triple::x86_64)
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< Name << Triple.getArchName();
-} else if (Name == "libmvec") {
+
@@ -389,7 +389,7 @@ ENUM_CODEGENOPT(Inlining, InliningMethod, 2, NormalInlining)
VALUE_CODEGENOPT(InlineMaxStackSize, 32, UINT_MAX)
// Vector functions library to use.
-ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibrary::NoLibrary)
+ENUM_CODEG
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paulwalker-arm wrote:
Rebased to incorporate https://github.com/llvm/llvm-project/pull/139190. Thanks
again @topperc.
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@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF,
llvm::FixedVectorType *ToTy,
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, first bitcast the source.
if (FromTy->getElementType()->isIntegerTy(1) &&
- FromTy->getElemen
@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF,
llvm::FixedVectorType *ToTy,
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, first bitcast the source.
if (FromTy->getElementType()->isIntegerTy(1) &&
- FromTy->getElemen
https://github.com/paulwalker-arm approved this pull request.
This looks good to me. Thanks for helping to unblock
https://github.com/llvm/llvm-project/pull/130973 @topperc.
https://github.com/llvm/llvm-project/pull/139190
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@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF,
llvm::FixedVectorType *ToTy,
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, first bitcast the source.
if (FromTy->getElementType()->isIntegerTy(1) &&
- FromTy->getElemen
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@@ -1366,19 +1366,29 @@ static llvm::Value *CreateCoercedLoad(Address Src,
llvm::Type *Ty,
// If we are casting a fixed i8 vector to a scalable i1 predicate
// vector, use a vector insert and bitcast the result.
if (ScalableDstTy->getElementType()->isIntegerT
@@ -2517,8 +2527,17 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) {
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, bitcast the source and use a vector extract.
if (ScalableSrcTy->getElementType()->isIntegerTy(1) &
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@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF,
llvm::FixedVectorType *ToTy,
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, first bitcast the source.
if (FromTy->getElementType()->isIntegerTy(1) &&
- FromTy->getElemen
https://github.com/paulwalker-arm commented:
This looks broadly good to me.
https://github.com/llvm/llvm-project/pull/139190
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https://github.com/llvm/llvm-project/pull/139236
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This is exactly the way to go.
https://github.com/llvm/llvm-project/pull/139236
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@@ -25030,7 +25030,8 @@ static SDValue foldCSELofLASTB(SDNode *Op, SelectionDAG
&DAG) {
if (AnyPred.getOpcode() == AArch64ISD::REINTERPRET_CAST)
AnyPred = AnyPred.getOperand(0);
- if (TruePred != AnyPred && TruePred.getOpcode() != AArch64ISD::PTRUE)
+ if (TruePred !=
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@@ -5464,6 +5464,15 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
Builder.CreateStore(errorValue, swiftErrorTemp);
}
+// Mfloat8 type is loaded as scalar type, but is treated as single
+// vector type for other operation
@@ -4179,9 +4183,19 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const CallExpr
*E,
unsigned IntrinsicID,
bool IsZExtReturn) {
QualType LangPTy = E->getArg(1)->getType();
- llvm::Type *MemEl
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@@ -4226,9 +4242,21 @@ Value *CodeGenFunction::EmitSVEMaskedStore(const
CallExpr *E,
SmallVectorImpl &Ops,
unsigned IntrinsicID) {
QualType LangPTy = E->getArg(1)->getType();
- llvm::Type
@@ -4179,9 +4183,21 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const CallExpr
*E,
unsigned IntrinsicID,
bool IsZExtReturn) {
QualType LangPTy = E->getArg(1)->getType();
- llvm::Type *MemEl
https://github.com/paulwalker-arm approved this pull request.
I've not verified every line of the test files but what I've seen looks good,
as do the code changes. Other than a few stylistic suggestions this looks good
to me.
https://github.com/llvm/llvm-project/pull/128019
__
@@ -4179,9 +4183,21 @@ Value *CodeGenFunction::EmitSVEMaskedLoad(const CallExpr
*E,
unsigned IntrinsicID,
bool IsZExtReturn) {
QualType LangPTy = E->getArg(1)->getType();
- llvm::Type *MemEl
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@@ -1360,8 +1360,15 @@ void
TargetLibraryInfoImpl::addVectorizableFunctionsFromVecLib(
addVectorizableFunctions(VecFuncs_DarwinLibSystemM);
break;
}
- case LIBMVEC_X86: {
-addVectorizableFunctions(VecFuncs_LIBMVEC_X86);
+ case LIBMVEC: {
+switch (TargetTrip
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@@ -29,7 +29,7 @@ static cl::opt
ClVectorLibrary(
"Accelerate framework"),
clEnumValN(TargetLibraryInfoImpl::DarwinLibSystemM,
"Darwin_libsystem_m", "Darwin libsystem_m"),
- clEnumValN(TargetLibra
paulwalker-arm wrote:
Re-review request after rebasing to pull in driver fix.
https://github.com/llvm/llvm-project/pull/138262
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>From 5da6f3e5ff07977294d82721c4bd37984daace47 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Fri, 2 May 2025 12:41:06 +0100
Subject: [PATCH 1/2] Add test showing x86 functions when targeting AArch64.
https://github.com/paulwalker-arm closed
https://github.com/llvm/llvm-project/pull/138288
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@@ -5464,6 +5464,15 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
Builder.CreateStore(errorValue, swiftErrorTemp);
}
+// Mfloat8 type is loaded as scalar type, but is treated as single
+// vector type for other operation
@@ -2056,9 +2056,21 @@ void NeonEmitter::createIntrinsic(const Record *R,
auto &Entry = IntrinsicMap[Name];
for (auto &I : NewTypeSpecs) {
+
+// MFloat8 type is only available on AArch64. If encountered set ArchGuard
+// correctly.
+std::string savedArchGuard =
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paulwalker-arm wrote:
Yep, that looks broken as well. I'll update the PR. I've done a grep for
`OPT_fveclib` and I don't see any other uses so hopefully this is the last one.
https://github.com/llvm/llvm-project/pull/138288
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@@ -934,7 +934,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const
ArgList &Args,
std::optional OptVal =
llvm::StringSwitch>(ArgVecLib->getValue())
.Case("Accelerate", "Accelerate")
-.Case("LIBMVEC", "LIBMVEC-X86")
+
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/138288
There are various places where the -fveclib option is parsed to determine
whether its value is correct for the target. Unfortunately these places assume
case-insensitivity and subsequently use "LIBMVEC"
@@ -26,11 +26,15 @@ typedef vbool64_t fixed_bool64_t
__attribute__((riscv_rvv_vector_bits(__riscv_v_
//
// CHECK-128-LABEL: @call_bool32_ff(
// CHECK-128-NEXT: entry:
+// CHECK-128-NEXT:[[SAVED_VALUE:%.*]] = alloca <1 x i8>, align 1
paulwalker-arm wrote:
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@@ -554,6 +554,22 @@ class VectorType : public Type {
return VectorType::get(VTy->getElementType(), EltCnt * 2);
}
+ /// This static method returns a VectorType with the same size-in-bits as
+ /// SizeTy but with an element type that matches the scalar type of EltTy.
-
@@ -554,6 +554,22 @@ class VectorType : public Type {
return VectorType::get(VTy->getElementType(), EltCnt * 2);
}
+ /// This static method returns a VectorType with the same size-in-bits as
+ /// SizeTy but with an element type that matches the scalar type of EltTy.
+
@@ -1168,6 +1168,15 @@ bool Function::nullPointerIsDefined() const {
return hasFnAttribute(Attribute::NullPointerIsValid);
}
+unsigned Function::getVScaleValue() const {
+ Attribute Attr = getFnAttribute(Attribute::VScaleRange);
+ if (!Attr.isValid())
+return 0;
+
+ u
@@ -80,7 +80,9 @@ fixed_bool32_t from_vbool32_t(vbool32_t type) {
//
// CHECK-128-LABEL: @to_vbool32_t(
// CHECK-128-NEXT: entry:
-// CHECK-128-NEXT:ret [[TYPE_COERCE:%.*]]
+// CHECK-128-NEXT:[[SAVED_VALUE:%.*]] = alloca <1 x i8>, align 1
+// CHECK-128-NEXT:
[[SAV
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/130973
>From 32a2805a41dc3ff02bff9df26f4665923445b488 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 20 Mar 2025 14:58:51 +
Subject: [PATCH 1/4] Add SROA tests for casts between fixed and scalable
ty
paulwalker-arm wrote:
> @paulwalker-arm the reasoning behind creating separate records, is that
> mfloat type is not available for aarch32 architectures and therefore all
> intrinsics using it need to be gated behind `ArchGuard =
> "defined(__aarch64__)"` .
I see. How practical would it be f
paulwalker-arm wrote:
ping
https://github.com/llvm/llvm-project/pull/130973
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@@ -5464,6 +5464,15 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
Builder.CreateStore(errorValue, swiftErrorTemp);
}
+// Mfloat8 type is loaded as scalar type, but is treated as single
+// vector type for other operation
paulwalker-arm wrote:
For my education can you explain why the fp8 variants are broken out into their
own definitions. Taking `VREV64_MF8` as an example, it looks like you should
be able to add the new type strings to the current definition?
https://github.com/llvm/llvm-project/pull/128019
__
@@ -554,6 +554,22 @@ class VectorType : public Type {
return VectorType::get(VTy->getElementType(), EltCnt * 2);
}
+ /// This static method returns a VectorType with the same size-in-bits as
+ /// SizeTy but with an element type that matches the scalar type of EltTy.
+
@@ -1990,21 +2028,56 @@ static bool canConvertValue(const DataLayout &DL, Type
*OldTy, Type *NewTy) {
static Value *convertValue(const DataLayout &DL, IRBuilderTy &IRB, Value *V,
Type *NewTy) {
Type *OldTy = V->getType();
- assert(canConvertValue(
https://github.com/paulwalker-arm commented:
I'll take a closer look later but here are some stylistic things to streamline
the patch a little.
https://github.com/llvm/llvm-project/pull/135016
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ht
@@ -1492,9 +1492,17 @@ static bool isAllActivePredicate(Value *Pred) {
if (cast(Pred->getType())->getMinNumElements() <=
cast(UncastedPred->getType())->getMinNumElements())
Pred = UncastedPred;
+ if (match(Pred, m_Intrinsic(
+ m_ConstantI
@@ -2641,6 +2641,20 @@ static std::optional
instCombineDMB(InstCombiner &IC,
return std::nullopt;
}
+static std::optional instCombinePTrue(InstCombiner &IC,
+ IntrinsicInst &II) {
+ IRBuilder<> Builder(&II);
+ auto Type
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/135016
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@@ -2641,6 +2641,20 @@ static std::optional
instCombineDMB(InstCombiner &IC,
return std::nullopt;
}
+static std::optional instCombinePTrue(InstCombiner &IC,
+ IntrinsicInst &II) {
+ IRBuilder<> Builder(&II);
+ auto Type
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/135016
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https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/130973
>From 32a2805a41dc3ff02bff9df26f4665923445b488 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 20 Mar 2025 14:58:51 +
Subject: [PATCH 1/2] Add SROA tests for casts between fixed and scalable
ty
@@ -2034,6 +2071,18 @@ static Value *convertValue(const DataLayout &DL,
IRBuilderTy &IRB, Value *V,
}
}
+ if (isa(NewTy) && isa(OldTy)) {
+auto *Ty = VectorType::getWithSizeAndScalar(cast(NewTy),
OldTy);
+V = IRB.CreateInsertVector(Ty, PoisonValue::get(Ty), V,
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