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https://github.com/llvm/llvm-project/pull/152547
Only set a target guard if it deviates from its default value[1].
When a target guard is set, it is automatically AND'd with its default value.
This means there is no need to use SVETargetGuard="sve,bf16
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p2 < %s | FileCheck %s
--check-prefixes=CHECK
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2p2 < %s | FileCheck %s
--check-
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@@ -594,13 +602,29 @@ define @dupq_i64_range( %a) {
;
define dso_local @dupq_f32_repeat_complex(float %x, float
%y) {
-; CHECK-LABEL: dupq_f32_repeat_complex:
-; CHECK: // %bb.0:
-; CHECK-NEXT:// kill: def $s0 killed $s0 def $z0
-; CHECK-NEXT:// kill: def $s1
@@ -980,8 +980,8 @@ defm SVCLASTA_N : SVEPerm<"svclasta[_n_{d}]", "sPsd",
"aarch64_sve_clasta_n">;
defm SVCLASTB : SVEPerm<"svclastb[_{d}]", "dPdd", "aarch64_sve_clastb">;
defm SVCLASTB_N : SVEPerm<"svclastb[_n_{d}]", "sPsd", "aarch64_sve_clastb_n">;
-let SVETargetGuard =
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN: -target-feature +sve -target-feature +sme -target-feature +ssve
-target-feature +sme2p2 \
paulwalker-arm wrote:
Does the target feature "+ssve" exist?
That said, given my next comm
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
--check-prefixes=CHECK,SVE
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
--check-prefix
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p2 < %s | FileCheck %s
--check-prefixes=CHECK
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2p2 < %s | FileCheck %s
--check-
@@ -980,8 +980,9 @@ defm SVCLASTA_N : SVEPerm<"svclasta[_n_{d}]", "sPsd",
"aarch64_sve_clasta_n">;
defm SVCLASTB : SVEPerm<"svclastb[_{d}]", "dPdd", "aarch64_sve_clastb">;
defm SVCLASTB_N : SVEPerm<"svclastb[_n_{d}]", "sPsd", "aarch64_sve_clastb_n">;
-let SVETargetGuard =
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN: -target-feature +sve -target-feature +sme -target-feature +ssve
-target-feature +sme2p2 \
+// RUN: -fsyntax-only -verify %s
+// REQUIRES: aarch64-registered-target
+// expected-no-diagnostics
+
+
+
https://github.com/paulwalker-arm commented:
Can you confirm you're intentionally ignoring the byte and halfword variants of
compact that are also available with +sme2p2? This works for me, I just want to
make sure I'm reviewing the PR properly.
https://github.com/llvm/llvm-project/pull/151703
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@@ -1,87 +0,0 @@
-// REQUIRES: aarch64-registered-target
-
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -verify
-verify-ignore-unexpected=error,note -emit-llvm -o - %s
-
-#include
-
-void test_bfloat(svbool_t pg, uint64_t u64, int64_t i64, const bfloat
@@ -1,87 +0,0 @@
-// REQUIRES: aarch64-registered-target
-
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -verify
-verify-ignore-unexpected=error,note -emit-llvm -o - %s
-
-#include
-
-void test_bfloat(svbool_t pg, uint64_t u64, int64_t i64, const bfloat
@@ -1,12 +1,12 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature
+sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emi
@@ -1,87 +0,0 @@
-// REQUIRES: aarch64-registered-target
-
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -verify
-verify-ignore-unexpected=error,note -emit-llvm -o - %s
-
-#include
-
-void test_bfloat(svbool_t pg, uint64_t u64, int64_t i64, const bfloat
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@@ -241,34 +231,17 @@ def SVLDNF1SW_VNUM : MInst<"svldnf1sw_vnum_{d}", "dPUl",
"lUl", [IsL
def SVLDNF1UW_VNUM : MInst<"svldnf1uw_vnum_{d}", "dPYl", "lUl",
[IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnf1">;
} // let SVETargetGuard = "sve", S
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@@ -370,8 +370,11 @@ def FeatureSVEAES : ExtensionWithMArch<"sve-aes", "SVEAES",
def FeatureAliasSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
"", "Shorthand for +sve2+sve-aes", [FeatureSVE2, FeatureSVEAES]>;
-def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM
https://github.com/paulwalker-arm updated
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>From 4efe257b27e6a76740a425ca93dd35cfac38919b Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 26 Jun 2025 17:28:11 +0100
Subject: [PATCH] [Clang][AArch64] Fix feature guards for SVE2p1 builtins
av
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@@ -264,22 +264,22 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard =
"sme,bf16" in {
def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc", "b", MergeNone,
"aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
}
-multiclass StructLoad {
- def : SInst;
+multiclass StructLoad f =
[]> {
+
@@ -264,22 +264,22 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard =
"sme,bf16" in {
def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc", "b", MergeNone,
"aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
}
-multiclass StructLoad {
- def : SInst;
+multiclass StructLoad f =
[]> {
+
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@@ -569,34 +569,39 @@ static bool checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
// * When compiling for SVE only, the caller must be in non-streaming mode.
// * When compiling for both SVE and SME, the caller can be in either mode.
if (BuiltinType == SemaARM::Veri
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https://github.com/llvm/llvm-project/pull/147086
Builtins that are enabled via +sve2p1 in non-streaming mode and +sme{2} in
streaming mode should also be enabled via +sve+sme{2} in non-streaming mode and
+sme+sve2p1 in streaming mode.
>From ac5fe90692
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https://github.com/llvm/llvm-project/pull/146353
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ping
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@@ -3487,7 +3487,8 @@ def fno_experimental_isel : Flag<["-"],
"fno-experimental-isel">, Group;
def fveclib : Joined<["-"], "fveclib=">, Group,
Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>,
-HelpText<"Use the given vector functions library">,
+HelpText<
@@ -2082,8 +2082,13 @@ const StringMap sys::getHostCPUFeatures() {
.Case("fp", "fp-armv8")
.Case("crc32", "crc")
.Case("atomics", "lse")
+
@@ -330,3 +330,6 @@ mfloat8x8_t test_vcvt_mf8_f16_fpm(float16x4_t vn,
float16x4_t vm, fpm_t fpm) {
mfloat8x16_t test_vcvtq_mf8_f16_fpm(float16x8_t vn, float16x8_t vm, fpm_t fpm)
{
return vcvtq_mf8_f16_fpm(vn, vm, fpm);
}
+
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64)
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/145941
Rather than filtering the calling function's features the PR splits the builtin
guard into distinct non-streaming and streaming guards that are compared to the
active features in full.
This has no affec
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paulwalker-arm wrote:
> Thanks for your excellent work! I'll add the same support to Flang. If you
> (or anyone) are already working on this, please let me know.
Nobody on our side is working on this. Thanks in advance.
https://github.com/llvm/llvm-project/pull/143696
_
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/145696
Adds sve-sha3 to reference FEAT_SVE_SHA3 without specifically enabling SVE2.
The SVE2 requirement for AES, SHA3 and Bitperm is replaced with SVE for
non-streaming function.
>From 565d4f767f2abee3d626900
https://github.com/paulwalker-arm approved this pull request.
The documentation build failure has been verified locally as an existing
upstream issue and not the fault of this PR.
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@@ -237,6 +237,266 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVdN4v_log",
FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8), "_ZGV_LLVM_N8v")
+#elif defined(TLI
@@ -237,6 +237,266 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVdN4v_log",
FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8), "_ZGV_LLVM_N8v")
+#elif defined(TLI
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https://github.com/paulwalker-arm commented:
I could not spot any tests for the `<2 x float>` vector functions? Hopefully
it's as easy as adding extra RUN lines to veclib-function-calls.ll and
veclib-intrinsic-calls.ll. I'm thinking variants of LIBMVEC-NEON that use
`-force-vector-width=2`. I
@@ -237,6 +237,266 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVdN4v_log",
FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8), "_ZGV_LLVM_N8v")
+#elif defined(TLI
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@@ -1299,6 +1299,30 @@ static const VecDesc VecFuncs_LIBMVEC_X86[] = {
#undef TLI_DEFINE_LIBMVEC_X86_VECFUNCS
};
+static const VecDesc VecFuncs_LIBMVEC_AARCH64_VF2[] = {
+#define TLI_DEFINE_LIBMVEC_AARCH64_VF2_VECFUNCS
+#define TLI_DEFINE_VECFUNC(SCAL, VEC, VABI_PREFIX)
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@@ -1299,6 +1299,30 @@ static const VecDesc VecFuncs_LIBMVEC_X86[] = {
#undef TLI_DEFINE_LIBMVEC_X86_VECFUNCS
};
+static const VecDesc VecFuncs_LIBMVEC_AARCH64_VF2[] = {
+#define TLI_DEFINE_LIBMVEC_AARCH64_VF2_VECFUNCS
+#define TLI_DEFINE_VECFUNC(SCAL, VEC, VABI_PREFIX)
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@@ -1299,6 +1299,30 @@ static const VecDesc VecFuncs_LIBMVEC_X86[] = {
#undef TLI_DEFINE_LIBMVEC_X86_VECFUNCS
};
+static const VecDesc VecFuncs_LIBMVEC_AARCH64_VF2[] = {
+#define TLI_DEFINE_LIBMVEC_AARCH64_VF2_VECFUNCS
+#define TLI_DEFINE_VECFUNC(SCAL, VEC, VABI_PREFIX)
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@@ -177,16 +177,16 @@ define void @add_unique_ind32(ptr noalias nocapture %a,
i64 %n) {
; CHECK-LABEL: @add_unique_ind32(
; CHECK-NEXT: entry:
; CHECK-NEXT:[[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT:[[TMP1:%.*]] = shl i64 [[TMP0]], 2
+; CHECK-NEXT:[[
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>From e2642bec52f881c1d457f2c72ed3ae4ceec570e6 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 20 Mar 2025 14:58:51 +
Subject: [PATCH 1/3] Add SROA tests for casts between fixed and scalable
ty
@@ -4793,11 +4793,7 @@ Value
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
case SVE::BI__builtin_sve_svlen_u64: {
SVETypeFlags TF(Builtin->TypeModifier);
auto VTy = cast(getSVEType(TF));
paulwalker-arm wrote:
It turns out `getSVETy
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/142803
>From 0819cda292ccc0fa7376bb4c78d4884cf5845410 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Wed, 4 Jun 2025 13:06:31 +0100
Subject: [PATCH 1/2] [NFC][LLVM] Refactor
IRBuilder::Create{VScale,ElementCo
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/142803
CreateVScale took a scaling parameter that had a single use outside of
IRBuilder with all other callers having to create a redundant ConstantInt. To
work round this some code perferred to use CreateIntri
paulwalker-arm wrote:
ping
https://github.com/llvm/llvm-project/pull/130973
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https://github.com/paulwalker-arm approved this pull request.
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@@ -744,3 +744,38 @@
// CHECK-SMEB16B16: __ARM_FEATURE_SME2 1
// CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1
// CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1
+//
+// RUN: %clang --target=aarch64 -march=armv9-a+fp8 -x c -E -dM %s -o - |
FileCheck --check-prefix=CHECK-FP8 %s
+//
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https://github.com/paulwalker-arm commented:
Last question but otherwise this looks good to me.
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@@ -1046,6 +1082,29 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasSVEB16B16 = true;
HasSMEB16B16 = true;
}
+
+if (Feature == "+fp8")
+ HasFP8 = true;
+if (Feature == "+fp8fma")
+ HasFP8FMA = true;
+if (Feature =
@@ -1046,6 +1082,29 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasSVEB16B16 = true;
HasSMEB16B16 = true;
}
+
+if (Feature == "+fp8")
+ HasFP8 = true;
+if (Feature == "+fp8fma")
paulwalker-arm wrote:
`fp
@@ -744,3 +744,34 @@
// CHECK-SMEB16B16: __ARM_FEATURE_SME2 1
// CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1
// CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1
+//
+// RUN: %clang --target=aarch64 -march=armv9-a+fp8 -x c -E -dM %s -o - |
FileCheck --check-prefix=CHECK-FP8 %s
+//
@@ -1046,6 +1082,29 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasSVEB16B16 = true;
HasSMEB16B16 = true;
}
+
+if (Feature == "+fp8")
+ HasFP8 = true;
+if (Feature == "+fp8fma")
paulwalker-arm wrote:
I d
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@@ -744,3 +744,34 @@
// CHECK-SMEB16B16: __ARM_FEATURE_SME2 1
// CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1
// CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1
+//
+// RUN: %clang --target=aarch64 -march=armv9-a+fp8 -x c -E -dM %s -o - |
FileCheck --check-prefix=CHECK-FP8 %s
+//
@@ -5844,7 +5844,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Triple.getArch() != llvm::Triple::x86_64)
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< Name << Triple.getArchName();
-} else if (Name == "libmvec") {
+
@@ -389,7 +389,7 @@ ENUM_CODEGENOPT(Inlining, InliningMethod, 2, NormalInlining)
VALUE_CODEGENOPT(InlineMaxStackSize, 32, UINT_MAX)
// Vector functions library to use.
-ENUM_CODEGENOPT(VecLib, llvm::driver::VectorLibrary, 3,
llvm::driver::VectorLibrary::NoLibrary)
+ENUM_CODEG
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/130973
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UI,Helvetica,Arial
paulwalker-arm wrote:
Rebased to incorporate https://github.com/llvm/llvm-project/pull/139190. Thanks
again @topperc.
https://github.com/llvm/llvm-project/pull/130973
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@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF,
llvm::FixedVectorType *ToTy,
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, first bitcast the source.
if (FromTy->getElementType()->isIntegerTy(1) &&
- FromTy->getElemen
@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF,
llvm::FixedVectorType *ToTy,
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, first bitcast the source.
if (FromTy->getElementType()->isIntegerTy(1) &&
- FromTy->getElemen
https://github.com/paulwalker-arm approved this pull request.
This looks good to me. Thanks for helping to unblock
https://github.com/llvm/llvm-project/pull/130973 @topperc.
https://github.com/llvm/llvm-project/pull/139190
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@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF,
llvm::FixedVectorType *ToTy,
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, first bitcast the source.
if (FromTy->getElementType()->isIntegerTy(1) &&
- FromTy->getElemen
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/139190
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https://github.com/llvm/llvm-project/pull/139190
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https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/139190
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@@ -1366,19 +1366,29 @@ static llvm::Value *CreateCoercedLoad(Address Src,
llvm::Type *Ty,
// If we are casting a fixed i8 vector to a scalable i1 predicate
// vector, use a vector insert and bitcast the result.
if (ScalableDstTy->getElementType()->isIntegerT
@@ -2517,8 +2527,17 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) {
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, bitcast the source and use a vector extract.
if (ScalableSrcTy->getElementType()->isIntegerTy(1) &
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/139190
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@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF,
llvm::FixedVectorType *ToTy,
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, first bitcast the source.
if (FromTy->getElementType()->isIntegerTy(1) &&
- FromTy->getElemen
https://github.com/paulwalker-arm commented:
This looks broadly good to me.
https://github.com/llvm/llvm-project/pull/139190
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https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/139236
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https://github.com/llvm/llvm-project/pull/139236
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https://github.com/paulwalker-arm commented:
This is exactly the way to go.
https://github.com/llvm/llvm-project/pull/139236
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@@ -25030,7 +25030,8 @@ static SDValue foldCSELofLASTB(SDNode *Op, SelectionDAG
&DAG) {
if (AnyPred.getOpcode() == AArch64ISD::REINTERPRET_CAST)
AnyPred = AnyPred.getOperand(0);
- if (TruePred != AnyPred && TruePred.getOpcode() != AArch64ISD::PTRUE)
+ if (TruePred !=
https://github.com/paulwalker-arm edited
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