zqb-all wrote:
https://github.com/llvm/llvm-project/pull/111337
https://github.com/llvm/llvm-project/pull/104390
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https://github.com/zqb-all closed
https://github.com/llvm/llvm-project/pull/104390
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https://github.com/zqb-all created
https://github.com/llvm/llvm-project/pull/104390
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>From 434bc55536b239047ff094d6bee44c5f6b8e72ef Mon Sep 17 00:00:00 2001
From: Mark Zhuang
Date: Thu, 15 Aug 2024 10:25:37 +0800
Subject: [PATCH] [OpenMP] Require x86-registered-target for test use avx512
@@ -381,3 +381,21 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
zqb-all wrote:
LGTM. x60 also supports `svnapot`, and although it seems to have no impact on
compiler behavior, I see that it is defined in llvm and is part of RVA23, so it
might be worth adding it as well.
https://github.com/llvm/llvm-project/pull/94564
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zqb-all wrote:
Need to add zicond, which is not in RVA22S64Features
https://github.com/llvm/llvm-project/pull/94564
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zqb-all wrote:
> Spacemit K1 is the name of the product/SoC or whatever you call it. The
> processor definitions in the RISCV backend are focusing on the CPU core. For
> Spacemit K1, the name of its core should be `X60`? I don't know……
Yes，core is x60: https://www.spacemit.com/spacemit-x60-co
