FreddyLeaf wrote:
> Looks like this breaks tests: http://45.33.8.238/linux/153081/step_6.txt
>
> Please take a look and revert for now if it takes a while to fix.
Thanks reminding. Revert first.
https://github.com/llvm/llvm-project/pull/113881
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https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/116564
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From 043c82617a6b1aec08915f294b8ede449705b09d Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 18 Nov 2024 08:47:24 +0800
Subject: [PATCH] Reland "
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/116563
This reverts commit 826b845c9e97448395431be3e4e5da585bd98c5e.
>From e349e24b3e10a44414593252d117bf2936b4bc91 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 18 Nov 2024 08:43:26 +0800
Subject: [PATCH] R
https://github.com/FreddyLeaf closed
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@@ -1155,6 +1155,34 @@ def ProcessorFeatures {
list GNRDFeatures =
!listconcat(GNRFeatures, GNRDAdditionalFeatures);
+ // Diamond Rapids
+ list DMRAdditionalFeatures = [FeatureAVX10_2_512,
+ FeatureAMXCOMPLEX,
--
@@ -381,6 +389,8 @@ constexpr ProcInfo Processors[] = {
{ {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16,
FeaturesSapphireRapids, 'n', false },
// Clearwaterforest microarchitecture based processors.
{ {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2,
FeaturesC
@@ -121,6 +121,7 @@ enum CPUKind {
CK_GraniterapidsD,
CK_Emeraldrapids,
CK_Clearwaterforest,
+ CK_DiamondRapids,
FreddyLeaf wrote:
ab477fb
https://github.com/llvm/llvm-project/pull/113881
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https://github.com/llvm/llvm-project/pull/113881
>From 4a7f17f29a007ce7af0893670a362f738b0d8d6e Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 15:27:24 +0800
Subject: [PATCH 1/6] [X86] Support -march=diamondrapids
Ref.: https://cdrdv2.inte
@@ -121,6 +121,7 @@ enum CPUKind {
CK_GraniterapidsD,
CK_Emeraldrapids,
CK_Clearwaterforest,
+ CK_DiamondRapids,
FreddyLeaf wrote:
I prefer your style, too. Let's refine CK_SapphireRapids as well in the future
https://github.com/llvm/llvm-project/pull/
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/113881
>From 4a7f17f29a007ce7af0893670a362f738b0d8d6e Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 15:27:24 +0800
Subject: [PATCH 1/5] [X86] Support -march=diamondrapids
Ref.: https://cdrdv2.inte
@@ -600,6 +601,19 @@ static const char
*getIntelProcessorTypeAndSubtype(unsigned Family,
break;
}
break;
+ case 19:
+switch (Model) {
+// Diamondrapids:
+case 0x01:
+ CPU = "diamondrapids";
+ *Type = INTEL_COREI7;
+ *Subtype = INTEL_CO
@@ -1139,6 +1139,28 @@ def ProcessorFeatures {
list GNRDFeatures =
!listconcat(GNRFeatures, GNRDAdditionalFeatures);
+ // Diamondrapids
FreddyLeaf wrote:
[52e63a0](https://github.com/llvm/llvm-project/pull/113881/commits/52e63a0f4b48ad106471343f2f48976
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/114367
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@@ -10,3 +10,7 @@ int test_cmpccxadd32(void *__A, int __B, int __C) {
long long test_cmpccxadd64(void *__A, long long __B, long long __C) {
return _cmpccxadd_epi64(__A, __B, __C, 16); // expected-error {{argument
value 16 is outside the valid range [0, 15]}}
}
+
+long long t
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/114367
>From 4c0a5729c8da644cfc01ad25820386f0cc289316 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 25 Oct 2024 10:00:16 +0800
Subject: [PATCH 1/2] [X86][CFE] Correct parameter type of _cmpccxadd_epi64
---
c
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/113881
>From 4a7f17f29a007ce7af0893670a362f738b0d8d6e Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 15:27:24 +0800
Subject: [PATCH 1/2] [X86] Support -march=diamondrapids
Ref.: https://cdrdv2.inte
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/113881
>From 4a7f17f29a007ce7af0893670a362f738b0d8d6e Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 15:27:24 +0800
Subject: [PATCH 1/3] [X86] Support -march=diamondrapids
Ref.: https://cdrdv2.inte
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/113881
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From 4a7f17f29a007ce7af0893670a362f738b0d8d6e Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 15:27:24 +0800
Subject: [PATCH] [X86] Su
https://github.com/FreddyLeaf closed
https://github.com/llvm/llvm-project/pull/113402
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@@ -665,6 +665,9 @@ _storebe_i64(void * __P, long long __D) {
#include
#include
#include
+#if (defined(__SM4__))
FreddyLeaf wrote:
[c0a33ab](https://github.com/llvm/llvm-project/pull/113402/commits/c0a33abe804bafe11e9dcecb092b924bcd08cdb7)
https://github.c
@@ -0,0 +1,170 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
--check-prefixes=ATT
FreddyLeaf wrote:
[23d4bfc](https://github.com/llvm/llvm-project/pull/113402/commits/23d4bfcabdca8968cba600e2fc0b440121990ef5)
https://github.com/llvm/llvm-pro
@@ -261,6 +261,7 @@ X86_FEATURE_COMPAT(AVX10_1, "avx10.1-256",
36)
X86_FEATURE_COMPAT(AVX10_1_512, "avx10.1-512", 37)
X86_FEATURE_COMPAT(AVX10_2, "avx10.2-256",0)
X86_FEATURE_COMPAT(AVX10_2_512, "avx10.2-512",
@@ -2339,6 +2339,19 @@ TARGET_BUILTIN(__builtin_ia32_vfmaddnepbh512,
"V32yV32yV32yV32y", "ncV:512:", "a
TARGET_BUILTIN(__builtin_ia32_vfmaddnepbh256, "V16yV16yV16yV16y", "ncV:256:",
"avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vfmaddnepbh128, "V8yV8yV8yV8y", "ncV:128:",
"avx1
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/113274
>From 19c6400ac7127860ac1712941acbd1585614d17d Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 10:24:14 +0800
Subject: [PATCH 1/6] [X86] Support MOVRS and AVX10.2 instructions.
Ref.: https://
@@ -0,0 +1,170 @@
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s
--check-prefixes=ATT
FreddyLeaf wrote:
[23d4bfc](https://github.com/llvm/llvm-project/pull/113402/commits/23d4bfcabdca8968cba600e2fc0b440121990ef5)
https://github.com
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/113274
>From 19c6400ac7127860ac1712941acbd1585614d17d Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 10:24:14 +0800
Subject: [PATCH 1/5] [X86] Support MOVRS and AVX10.2 instructions.
Ref.: https://
@@ -1647,3 +1647,23 @@ let isCodeGenOnly = 1, ForceDisassemble = 1,
hasSideEffects = 0 in
def : InstAlias<"vmovw.s\t{$src, $dst|$dst, $src}",
(VMOVZPWILo2PWIZrr2 VR128X:$dst, VR128X:$src), 0>;
}
+
+// SM4(EVEX)
+multiclass avx10_sm4_base {
+ // SM4_Base is
@@ -196,6 +196,8 @@ Changes to the X86 Backend
* Support ISA of `AVX10.2-256` and `AVX10.2-512`.
+* Support ISA of `SM4(EVEX)`.
FreddyLeaf wrote:
[23d4bfc](https://github.com/llvm/llvm-project/pull/113402/commits/23d4bfcabdca8968cba600e2fc0b440121990ef5)
ht
@@ -6109,6 +6109,12 @@ let TargetPrefix = "x86" in {
DefaultAttrsIntrinsic<[llvm_v8i32_ty],
[llvm_v8i32_ty, llvm_v8i32_ty],
[IntrNoMem]>;
+def int_x86_vsm4key4512 : ClangBuiltin<"__builtin_ia32_vsm4key4512">,
+Intrinsic<[llvm_v16i32_ty], [llvm_v1
@@ -6109,6 +6109,12 @@ let TargetPrefix = "x86" in {
DefaultAttrsIntrinsic<[llvm_v8i32_ty],
[llvm_v8i32_ty, llvm_v8i32_ty],
[IntrNoMem]>;
+def int_x86_vsm4key4512 : ClangBuiltin<"__builtin_ia32_vsm4key4512">,
+Intrinsic<[llvm_v16i32_ty], [llvm_v1
@@ -1647,3 +1647,23 @@ let isCodeGenOnly = 1, ForceDisassemble = 1,
hasSideEffects = 0 in
def : InstAlias<"vmovw.s\t{$src, $dst|$dst, $src}",
(VMOVZPWILo2PWIZrr2 VR128X:$dst, VR128X:$src), 0>;
}
+
+// SM4(EVEX)
+multiclass avx10_sm4_base {
+ // SM4_Base is
@@ -0,0 +1,224 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck
%s
FreddyLeaf wrote:
[23d4bfc](https://github.com/llvm/llvm-project/pull/113402/commits/23d4bfcabdca8968cba600e2fc0b440121990ef5)
https://github.com/llvm/llvm-proje
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-- --show-mc-encoding
-mattr=+sm4,+avx10.2-512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- --show-mc-enc
https://github.com/FreddyLeaf edited
https://github.com/llvm/llvm-project/pull/113402
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@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-- --show-mc-encoding
-mattr=+sm4,+avx10.2-512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- --show-mc-enc
@@ -261,6 +261,7 @@ X86_FEATURE_COMPAT(AVX10_1, "avx10.1-256",
36)
X86_FEATURE_COMPAT(AVX10_1_512, "avx10.1-512", 37)
X86_FEATURE_COMPAT(AVX10_2, "avx10.2-256",0)
X86_FEATURE_COMPAT(AVX10_2_512, "avx10.2-512",
@@ -0,0 +1,174 @@
+/*===-- movrs_avx10_2intrin.h - AVX512MOVRS intrinsics -===
FreddyLeaf wrote:
[567131c](https://github.com/llvm/llvm-project/pull/113274/commits/567131c8c265bd29dede1ad76dd1c52a4077b270)
https://github.com/llvm/llvm-project
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/113274
>From 19c6400ac7127860ac1712941acbd1585614d17d Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 10:24:14 +0800
Subject: [PATCH 1/4] [X86] Support MOVRS and AVX10.2 instructions.
Ref.: https://
@@ -0,0 +1,98 @@
+/*=== movrs_avx10_2_512intrin.h - AVX512MOVRS intrinsics ---===
FreddyLeaf wrote:
[567131c](https://github.com/llvm/llvm-project/pull/113274/commits/567131c8c265bd29dede1ad76dd1c52a4077b270)
https://github.com/llvm/llvm-project/
@@ -7572,3 +7572,42 @@ def int_x86_avx10_vfnmsub231nepbf16128 :
ClangBuiltin<"__builtin_ia32_vfnmsub231
DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v8bf16_ty,
llvm_v8bf16_ty, llvm_v8bf16_ty ],
[IntrNoMem]>;
}
+
+let TargetPrefix = "x86"
https://github.com/FreddyLeaf ready_for_review
https://github.com/llvm/llvm-project/pull/113274
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>From 19c6400ac7127860ac1712941acbd1585614d17d Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 10:24:14 +0800
Subject: [PATCH 1/3] [X86] Support MOVRS and AVX10.2 instructions.
Ref.: https://
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/113274
>From 19c6400ac7127860ac1712941acbd1585614d17d Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 10:24:14 +0800
Subject: [PATCH 1/2] [X86] Support MOVRS and AVX10.2 instructions.
Ref.: https://
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/113402
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From 83a2ef421831dec1790c3c6adf3141ed1ac9a0d5 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 09:30:26 +0800
Subject: [PATCH] [X86] Su
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/113274
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From 19c6400ac7127860ac1712941acbd1585614d17d Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 21 Oct 2024 10:24:14 +0800
Subject: [PATCH] [X86] Su
@@ -44,7 +44,7 @@ unsigned char _InterlockedCompareExchange128_rel(__int64
volatile *_Destination,
__int64 *_ComparandResult);
#endif
-#ifdef __x86_64__
+#ifdef __x86_64__ && !defined(__arm64ec__)
FreddyLeaf wr
@@ -44,7 +44,7 @@ unsigned char _InterlockedCompareExchange128_rel(__int64
volatile *_Destination,
__int64 *_ComparandResult);
#endif
-#ifdef __x86_64__
+#ifdef __x86_64__ && !defined(__arm64ec__)
FreddyLeaf wr
https://github.com/FreddyLeaf approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/109598
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@@ -205,7 +214,8 @@ bool X86ATTInstPrinter::printVecCompareInstr(const MCInst
*MI,
printwordmem(MI, CurOp--, OS);
else
printdwordmem(MI, CurOp--, OS);
- } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) {
+
@@ -205,7 +214,8 @@ bool X86ATTInstPrinter::printVecCompareInstr(const MCInst
*MI,
printwordmem(MI, CurOp--, OS);
else
printdwordmem(MI, CurOp--, OS);
- } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) {
+
@@ -153,7 +163,8 @@ const X86InstrFMA3Group *llvm::getFMA3Group(unsigned
Opcode, uint64_t TSFlags) {
((TSFlags & X86II::EncodingMask) == X86II::EVEX &&
((TSFlags & X86II::OpMapMask) == X86II::T8 ||
(TSF
https://github.com/FreddyLeaf closed
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FreddyLeaf wrote:
> Should we add folding in X86InstrFMA3Info.cpp?
yes, addressed in
[b9e35f0](https://github.com/llvm/llvm-project/pull/101603/commits/b9e35f050d6319ebd8da3c0f4cf5399dd03b3915)
https://github.com/llvm/llvm-project/pull/101603
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@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -147,11 +147,13 @@ set(x86_files
amxcomplexintrin.h
amxfp16intrin.h
amxintrin.h
+ avx10_2_512bf16intrin.h
avx10_2_512convertintrin.h
avx10_2_512minmaxintrin.h
avx10_2_512niintrin.h
avx10_2_512satcvtintrin.h
avx10_2convertintrin.h
+ avx10_2bf16intrin.h
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -0,0 +1,565 @@
+/*===--- avx10_2_512bf16intrin.h - AVX10-BF16 intrinsics -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache
@@ -7219,3 +7219,413 @@ def int_x86_avx10_mask_vcvtneph2hf8s512 :
ClangBuiltin<"__builtin_ia32_vcvtneph2
DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v32f16_ty, llvm_v32i8_ty,
llvm_i32_ty],
[IntrNoMem]>;
}
+
+//===
@@ -0,0 +1,1054 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64 -target-feature +avx10.2-512 -emit-llvm -o -
-Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-
@@ -0,0 +1,565 @@
+/*===--- avx10_2_512bf16intrin.h - AVX10-BF16 intrinsics -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache
https://github.com/FreddyLeaf edited
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@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -211,6 +211,12 @@ def X86CmpMaskCC :
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
SDTCisVec<1>, SDTCisSameAs<2, 1>,
SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
+
+def X86CmpMaskCC_Int :
+ SDTypeProfile<1
@@ -14836,6 +14837,9 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned
BuiltinID,
case X86::BI__builtin_ia32_vfmaddph512_mask:
case X86::BI__builtin_ia32_vfmaddph512_maskz:
case X86::BI__builtin_ia32_vfmaddph512_mask3:
+ case X86::BI__builtin_ia32_vfmaddnepbh128:
+
@@ -0,0 +1,1054 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64 -target-feature +avx10.2-512 -emit-llvm -o -
-Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-
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https://github.com/FreddyLeaf approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/104781
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@@ -617,7 +617,7 @@ constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureVAES | FeatureVPCLMULQDQ
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -624,3 +624,328 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -7089,3 +7089,133 @@ def int_x86_avx10_mask_vcvttps2iubs512 :
ClangBuiltin<"__builtin_ia32_vcvttps2iu
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty,
llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg>]>;
}
+
+//===
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -2217,6 +2217,50 @@ TARGET_BUILTIN(__builtin_ia32_vcvttps2ibs512_mask,
"V16UiV16fV16UiUsIi", "nV:512
TARGET_BUILTIN(__builtin_ia32_vcvttps2iubs128_mask, "V4UiV4fV4UiUc",
"nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvttps2iubs256_mask, "V8UiV8fV8UiUcIi",
"nV:25
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@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
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None
>From d5275ef5e6a4e34bdae6b9b505ba1aae3a9a2363 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 14 Aug 2024 19:45:21 +0800
Subject: [PATCH] [X86][MC] Remove CMPCCXADD's CondCode flavor.
---
clang/t
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