[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

camel-cdr wrote: > The ISA is specified in this document too > https://www.sifive.com/document-file/eic7700x-datasheet available here > https://www.sifive.com/boards/hifive-premier-p550 None of the documentation is consistant nor complete reguarding the ISA: * [Product Brief](https://www.sif

[clang] [llvm] [RISCV] Add -mcpu=sifive-p550. (PR #122164)

camel-cdr wrote: I thought the P550 was supposed to support RV64GCB, but that wouls require Zbs support, which isn't listed here. https://github.com/llvm/llvm-project/pull/122164 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.ll

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

camel-cdr wrote: > Presumably that (rather terse) sentence in the specification is that even, > say, RV64GC can check the macro and include riscv_vector.h, so that it can > then do `__attribute__((__target__(...)))` and use it in certain functions? Yes, thats the idea, otherwise it would be im

[clang] [clang][RISCV] Bump RVV intrinsic to version 1.0 (PR #116597)

camel-cdr wrote: Considering the define is guarded behind `if (ISAInfo->hasExtension("zve32x"))`, this doesn't seem to implement: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/382 https://github.com/llvm/llvm-project/pull/116597 ___ cfe-com

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

camel-cdr wrote: Ventana's Veyron V1 is called `veyron-v1` not `ventana-veyron-v1`, Qualcomm's oryon is `oryon-1`. >From existing names, it seems like just `ascalon-d8` would be expected. The >company prefixes seem to mostly be used for very short processor names: >`apple-m1`, `spacemit-x60`,

[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

camel-cdr wrote: Are the vrgather.vv numbers correct? Usually LMUL>1 vrgather is implemented by aplying a LMUL=1 vrgather LMUL^2 times. Since the LMUL=1 vrgather.vv takes a single cycle, I would've expected a 4 cycle LMUL=2 vrgather.vv instead of 12. 12 cycles is less than one element per cycle

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

camel-cdr wrote: Ah, thanks, that works. How can support for behavior be detected? The intrinsic spec says: > The `__riscv_v_intrinsic` macro is the C macro to test the compiler's support > for the RISC-V "V" extension intrinsics. and recommends using: ```c #ifdef __riscv_v_intrinsic #include

[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

camel-cdr wrote: FYI, the example code you shown doesn't compile anymore: https://godbolt.org/z/ooTWEGejf This feature is quite important, without it we can't compile in RVV by default in a lot of libraries, e.g. simdutf, flac, ... https://github.com/llvm/llvm-project/pull/83674 _

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: https://github.com/camel-cdr edited https://github.com/llvm/llvm-project/pull/90392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: @@ -0,0 +1,1489 @@ +//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: camel-cdr wrote: The execution unit layout does not match the current XiangShan master. Has the final execution unit layout been decided on? [earlier layout](https://github.com/OpenXiangShan/XiangShan/blob/e25e4d90505c592524b410b127fe611ac49

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

camel-cdr wrote: Has the target architecture been finalized? (As in what it should be, not necessarily the rtl) Just yesterday, there was a significant change in vector execution units: [before](https://github.com/OpenXiangShan/XiangShan/blob/e25e4d90505c592524b410b127fe611ac49a3adf/src/main/s