https://github.com/brendandahl closed
https://github.com/llvm/llvm-project/pull/108116
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https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/108116
>From 3b813cd5b0555e6b654f575140e4db9a57ed699a Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Tue, 10 Sep 2024 21:52:55 +
Subject: [PATCH 1/2] [WebAssembly] Change F16x8 extract lane to require
const
@@ -1888,18 +1888,15 @@ static __inline__ v128_t __FP16_FN_ATTRS
wasm_f16x8_splat(float __a) {
return (v128_t)__builtin_wasm_splat_f16x8(__a);
}
-static __inline__ float __FP16_FN_ATTRS wasm_f16x8_extract_lane(v128_t __a,
-
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/108116
Building with no optimizations resulted in failures since the lane constant
wasn't a constant in LLVM IR.
>From 3b813cd5b0555e6b654f575140e4db9a57ed699a Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Tu
https://github.com/brendandahl closed
https://github.com/llvm/llvm-project/pull/106465
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brendandahl wrote:
> Would it make sense to put these declarations behind `#ifdef __wasm_fp16__`
> so that they aren't declared if fp16 support isn't enabled?
I could do that, if that's preferred. I followed what the relaxed instructions
did and use the target attribute `__target__("fp16")`.
@@ -165,8 +165,9 @@ def F16x8 : Vec {
let prefix = "f16x8";
}
-// TODO: Include F16x8 here when half precision is better supported.
-defvar AllVecs = [I8x16, I16x8, I32x4, I64x2, F32x4, F64x2];
+// TODO: Remove StdVecs when the F16x8 works every where StdVecs is used.
---
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/106465
Getting this to work required a few additional changes:
- Add builtins for any instructions that can't be done with plain C currently.
- Add support for the saturating version of fp_to__I16x8. Other vector
https://github.com/brendandahl closed
https://github.com/llvm/llvm-project/pull/105434
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https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/105434
>From e992578b7269c365e619fe201e7cc703149c7067 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Tue, 20 Aug 2024 21:55:47 +
Subject: [PATCH] [WebAssembly] Change half-precision feature name to fp16.
Th
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/105434
>From fe8fc8201cd3ed5c2909ef512c55e70a30e14a5e Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Tue, 20 Aug 2024 21:55:47 +
Subject: [PATCH] [WebAssembly] Change half-precision feature name to fp16.
Th
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/105434
This better aligns with how the feature is being referred to and what runtimes
(V8) are calling it.
>From c4d120d4ec01f2af4e6ad748543ed195aa8f6721 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Tue, 20
https://github.com/brendandahl closed
https://github.com/llvm/llvm-project/pull/99388
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https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/99388
>From 8320b1f7f45f42363547cefb748627cfe1bb7af6 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Wed, 17 Jul 2024 20:10:20 +
Subject: [PATCH] [WebAssembly] Implement f16x8.replace_lane instruction.
Use a
@@ -702,6 +702,19 @@ defm "" : ReplaceLane;
defm "" : ReplaceLane;
defm "" : ReplaceLane;
+// For now use an instrinsic for f16x8.replace_lane instead of ReplaceLane
above
+// since LL generated with half type arguments is not well supported and
creates
bren
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/99388
Use a builtin and intrinsic until half types are better supported for
instruction selection.
>From a6d65f276fba7487fdecf2e31edef457f74fbafe Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Wed, 17 Jul 2024
https://github.com/brendandahl closed
https://github.com/llvm/llvm-project/pull/95151
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brendandahl wrote:
Note: I've [opened an
issue](https://github.com/WebAssembly/half-precision/issues/5) about the
`relaxed_` prefix and whether it should be included in the instruction name.
https://github.com/llvm/llvm-project/pull/95151
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https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/95151
Implemented with intrinsics and builtins.
Specified at:
https://github.com/WebAssembly/half-precision/blob/main/proposals/half-precision/Overview.md
>From fd5ea6036e97e504e3286d218fe6b966e5bead82 Mon Sep 17
https://github.com/brendandahl closed
https://github.com/llvm/llvm-project/pull/93360
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@@ -1199,6 +1213,7 @@ def : Pat<(v2f64 (froundeven (v2f64 V128:$src))),
(NEAREST_F64x2 V128:$src)>;
multiclass SIMDBinaryFP
baseInst> {
defm "" : SIMDBinary;
defm "" : SIMDBinary;
+ defm "" : SIMDBinary;
brendandahl wrote:
I ended up adding `HalfPrecisi
@@ -152,6 +153,18 @@ def F64x2 : Vec {
let prefix = "f64x2";
}
+def F16x8 : Vec {
+ let vt = v8f16;
+ let int_vt = v8i16;
+ let lane_vt = f32;
+ let lane_rc = F32;
+ let lane_bits = 16;
+ let lane_idx = LaneIdx8;
+ let lane_load = int_wasm_loadf16_f32;
+ let splat = PatFrag<
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/93360
>From c33801afebb6720bc4b51fb4064b59529c40d298 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Thu, 23 May 2024 23:38:51 +
Subject: [PATCH 1/2] [WebAssembly] Implement all f16x8 binary instructions.
Th
https://github.com/brendandahl edited
https://github.com/llvm/llvm-project/pull/93360
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https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/93360
This reuses most of the code that was created for f32x4 and f64x2 binary
instructions and tries to follow how they were implemented.
add/sub/mul/div - use regular LL instructions
min/max - use the minimum/ma
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/93272
Specified at:
https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md
Note: the current spec has f16x8.extract_lane as opcode 0x124, bu
brendandahl wrote:
> LGTM % `!HasHalfPrecision` thing
>
> By the way I guess you can try getting commit access soon? I think it is
> still "Send an email to Chris" though...
Done, can I get a squash and merge?
I'll look into getting commit access.
https://github.com/llvm/llvm-project/pull/93
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/93228
>From 28cc678038feefffceba8cbe24349e1885b24c75 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Tue, 21 May 2024 21:15:14 +
Subject: [PATCH 1/2] [WebAssembly] Implement prototype f16x8.splat
instruction
@@ -90,6 +90,7 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public
TargetInfo {
StringRef getABI() const override;
bool setABI(const std::string &Name) override;
+ bool useFP16ConversionIntrinsics() const override { return false; }
brendandah
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/93228
>From 28cc678038feefffceba8cbe24349e1885b24c75 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Tue, 21 May 2024 21:15:14 +
Subject: [PATCH] [WebAssembly] Implement prototype f16x8.splat instruction.
Ad
brendandahl wrote:
cc @aheejin @dschuff
As mentioned in the meeting, it looks like it will be a lot more work to get
half value's working with normal patterns, so for now I'll stick to just
built-ins and intrinsics.
https://github.com/llvm/llvm-project/pull/93228
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/93228
Adds a builtin and intrinsic for the f16x8.splat instruction.
Specified at:
https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md
No
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/91545
>From adcb77e15d09f466f217d754f6f80aeb729aadc4 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Wed, 8 May 2024 23:10:07 +
Subject: [PATCH 1/5] [WebAssembly] Implement prototype f32.store_f16
instructio
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/91545
>From adcb77e15d09f466f217d754f6f80aeb729aadc4 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Wed, 8 May 2024 23:10:07 +
Subject: [PATCH 1/4] [WebAssembly] Implement prototype f32.store_f16
instructio
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/91545
>From adcb77e15d09f466f217d754f6f80aeb729aadc4 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Wed, 8 May 2024 23:10:07 +
Subject: [PATCH 1/3] [WebAssembly] Implement prototype f32.store_f16
instructio
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/91545
>From adcb77e15d09f466f217d754f6f80aeb729aadc4 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Wed, 8 May 2024 23:10:07 +
Subject: [PATCH 1/2] [WebAssembly] Implement prototype f32.store_f16
instructio
@@ -192,6 +192,7 @@
TARGET_BUILTIN(__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4, "V4fV8UsV8UsV4f"
// Half-Precision (fp16)
TARGET_BUILTIN(__builtin_wasm_loadf16_f32, "fh*", "nU", "half-precision")
+TARGET_BUILTIN(__builtin_wasm_storef16_f32, "vfh*", "nU", "half-precision")
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/91545
Adds a builtin and intrinsic for the f32.store_f16 instruction.
The instruction stores an f32 value as an f16 memory. Specified at:
https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc3
@@ -666,3 +666,29 @@ define {i32,i32,i32,i32} @aggregate_return() {
define {i64,i32,i16,i8} @aggregate_return_without_merge() {
ret {i64,i32,i16,i8} zeroinitializer
}
+
+;===
brendand
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/90906
>From 14313fa9ef33b4cbc8cf18f280ee885b38015ca4 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Wed, 1 May 2024 21:53:39 +
Subject: [PATCH 1/3] [WebAssembly] Implement prototype f32.load_f16
instruction
brendandahl wrote:
> Overall this looks good, and I think it makes sense to model this as short*
> for now. I think it will be interesting to see if that ends up causing
> issues. Out of curiosity does this work if you try `_fp16`?
I was trying _Float16 and that wasn't working since it require
@@ -38,6 +38,13 @@ multiclass RELAXED_I;
}
+multiclass HALF_PRECISION_I pattern_r, string asmstr_r = "",
+string asmstr_s = "", bits<32> simdop = -1> {
+ defm "" : ABSTRACT_SIMD_I;
+}
+
brendandahl wrote:
This will be for my next P
@@ -321,6 +321,18 @@ def int_wasm_relaxed_dot_bf16x8_add_f32:
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4f32_ty],
[IntrNoMem, IntrSpeculatable]>;
+//===--===//
+// Ha
brendandahl wrote:
/cc @tlively @dschuff
(I guess I can't assign reviewers since I don't have commit access.)
https://github.com/llvm/llvm-project/pull/90906
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https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/90906
>From 14313fa9ef33b4cbc8cf18f280ee885b38015ca4 Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Wed, 1 May 2024 21:53:39 +
Subject: [PATCH 1/2] [WebAssembly] Implement prototype f32.load_f16
instruction
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/90906
Adds a builtin and intrinsic for the f32.load_f16 instruction.
The instruction loads an f16 value from memory and puts it in an f32. Specified
at:
https://github.com/WebAssembly/half-precision/blob/29a9b9462
https://github.com/brendandahl updated
https://github.com/llvm/llvm-project/pull/90248
>From 85e5e1660ad1e6fda8ecf8984aab0cba96130b4f Mon Sep 17 00:00:00 2001
From: Brendan Dahl
Date: Fri, 26 Apr 2024 18:30:48 +
Subject: [PATCH] [WebAssembly] Add half-precision feature
This currently only
https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/90248
This currently only defines a constant, but in the future will be used to gate
builtins for experimenting and prototyping half-precision proposal
(https://github.com/WebAssembly/half-precision).
>From 09834
brendandahl wrote:
@efriedma-quic missed your comment. I don't have commit access. Can you merge
for me?
Thanks!
https://github.com/llvm/llvm-project/pull/66716
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brendandahl wrote:
@AaronBallman or @efriedma-quic ping are you able to add reviewers?
https://github.com/llvm/llvm-project/pull/66716
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brendandahl wrote:
@efriedma-quic could you re-review? The only changes were
https://github.com/llvm/llvm-project/pull/66716/files#diff-e724febedab9c1a2832bf2056d208ff02ddcb2e6f90b5a653afc9b19ac78a5d7R3098-R3100
https://github.com/llvm/llvm-project/pull/66716
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brendandahl wrote:
This is relanding the patch from [here](https://reviews.llvm.org/D156172). It
fixes the [backout
failure](https://reviews.llvm.org/rG88b7e06dcf9723d0869b0c6bee030b4140e4366d)
and adds a test for it.
https://github.com/llvm/llvm-project/pull/66716
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https://github.com/brendandahl created
https://github.com/llvm/llvm-project/pull/66716
Previously, annotations were only emitted for function definitions. With this
change annotations are also emitted for declarations. Also, emitting function
annotations is now deferred until the end so that t
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