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https://github.com/llvm/llvm-project/pull/122995
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https://github.com/AlexVlx commented:
> In this case I think just using the hardcoded 0 is less wrong than using the
> "LangAS::Default". This just happens to work out correctly for the OpenCL 1.x
> hack on amdgpu
I don't have a strong preference / that makes sense-ish but I was actually
le
AlexVlx wrote:
> > I don't think it makes any sense for `__has_builtin` to return true when
> > the target does not in-fact have the builtin. Most of the time this is used
> > to guard target specific code, which will then be wrong if it's compiled on
> > the device. Realistically the solution
AlexVlx wrote:
> `CodeGenHipStdPar/unsupported-builtins.cpp` is pretty interesting actually,
> it looks like it tests for some behavior in CodeGen that seems like it's
> trying to fix the exact same problem
>
> The other two tests seem to be actually unrelated breakages though.
It is not quit
@@ -814,7 +816,10 @@ static ABIArgInfo classifyType(CodeGenModule &CGM,
CanQualType type,
auto &layout = CGM.getContext().getASTRecordLayout(record);
if (mustPassRecordIndirectly(CGM, record))
- return ABIArgInfo::getIndirect(layout.getAlignment(), /*byval*/ fals
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/116820
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>From c5efdd24c0c889e26e3b00865780970ca5ed1f4c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 14:55:25 +
Subject: [PATCH 1/3] Translate `amdgpu_flat_work_group_size` into
`reqd_work_group_
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116820
>From c5efdd24c0c889e26e3b00865780970ca5ed1f4c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 14:55:25 +
Subject: [PATCH 1/3] Translate `amdgpu_flat_work_group_size` into
`reqd_work_group_
@@ -21,9 +21,12 @@ ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty)
const {
// Records with non-trivial destructors/copy-constructors should not be
// passed by value.
if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
- return getN
@@ -49,6 +49,8 @@ class ABIInfo {
CodeGen::CodeGenTypes &CGT;
llvm::CallingConv::ID RuntimeCC;
+ unsigned getTargetDefaultAS() const;
AlexVlx wrote:
Sure, but I couldn't quite figure out any other convenient, accessible,
non-intrusive place to stash thi
@@ -245,6 +247,41 @@
SPIRVTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
return DefaultGlobalAS;
}
+void SPIRVTargetCodeGenInfo::setTargetAttributes(
+const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
+ if (!M.getLangOpts().HIP |
@@ -245,6 +247,41 @@
SPIRVTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
return DefaultGlobalAS;
}
+void SPIRVTargetCodeGenInfo::setTargetAttributes(
+const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
+ if (!M.getLangOpts().HIP |
@@ -225,7 +225,9 @@ ABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty,
bool Variadic,
// Records with non-trivial destructors/copy-constructors should not be
// passed by value.
if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
- return getNaturalAlign
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/116820
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https://github.com/AlexVlx reopened
https://github.com/llvm/llvm-project/pull/116820
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https://github.com/llvm/llvm-project/pull/116820
>From c5efdd24c0c889e26e3b00865780970ca5ed1f4c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 14:55:25 +
Subject: [PATCH 1/3] Translate `amdgpu_flat_work_group_size` into
`reqd_work_group_
@@ -337,9 +337,12 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (hasFastFMA())
Builder.defineMacro("FP_FAST_FMA");
- Builder.defineMacro("__AMDGCN_WAVEFRONT_SIZE__", Twine(WavefrontSize));
- // ToDo: deprecate this macro for naming consistency
@@ -800,7 +800,9 @@ static ABIArgInfo classifyExpandedType(SwiftAggLowering
&lowering,
if (lowering.empty()) {
return ABIArgInfo::getIgnore();
} else if (lowering.shouldPassIndirectly(forReturn)) {
-return ABIArgInfo::getIndirect(alignmentForIndirect, /*byval*/ fal
@@ -225,7 +225,9 @@ ABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty,
bool Variadic,
// Records with non-trivial destructors/copy-constructors should not be
// passed by value.
if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
- return getNaturalAlign
AlexVlx wrote:
> I'm fine with how you're handling the address spaces for now.
>
> I'd like to talk about the rule you're implementing, though. It looks like
> it's supposed to be:
>
> * return values always use the alloca AS
> * arguments always use the default AS
> * whether something is ind
@@ -105,6 +105,11 @@ void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
if (!getCXXABI().classifyReturnType(FI))
FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
+ // srets / indirect returns are unconditionally in the alloca AS.
+ if (FI.getReturn
@@ -1350,7 +1350,7 @@ bool ItaniumCXXABI::classifyReturnType(CGFunctionInfo
&FI) const {
// If C++ prohibits us from making a copy, return by address.
if (!RD->canPassInRegisters()) {
auto Align = CGM.getContext().getTypeAlignInChars(FI.getReturnType());
-FI.getRet
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/11] `sret` args should always point to the `alloca` AS, so
we ca
@@ -92,6 +98,63 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/110897
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@@ -91,6 +97,100 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpa
https://github.com/AlexVlx requested changes to this pull request.
In principle I am against this, it adds a relatively brittle hook, and bypasses
the pre-existing mechanisms (use CL2 or enable the generic-as extension) for
obtaining this behaviour, in a way that does not ensure that the pre-ex
AlexVlx wrote:
Thank you for this, unfortunately I don't quite see the reason for adding
another twiddly bit here. We are long term migrating away from the
default-is-private hack, and to get the benefits you are looking for you can
simply compile for CL2, or enable the generic as extension, f
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/114481
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https://github.com/AlexVlx commented:
> #117410 gives you a way to do this without explicitly looking at the features
> or CPU
Cheers for this @arsenm, very useful; I've switched over to using it instead.
https://github.com/llvm/llvm-project/pull/114481
__
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/12] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/11] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
@@ -5158,14 +5155,17 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
} else if (!ReturnValue.isNull()) {
SRetPtr = ReturnValue.getAddress();
} else {
- SRetPtr = CreateMemTemp(RetTy, "tmp", &SRetAlloca);
+ SRetPtr = CreateMemTempWith
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/11] `sret` args should always point to the `alloca` AS, so
we ca
@@ -1350,7 +1350,7 @@ bool ItaniumCXXABI::classifyReturnType(CGFunctionInfo
&FI) const {
// If C++ prohibits us from making a copy, return by address.
if (!RD->canPassInRegisters()) {
auto Align = CGM.getContext().getTypeAlignInChars(FI.getReturnType());
-FI.getRet
@@ -296,18 +296,25 @@ void AggExprEmitter::withReturnValueSlot(
(RequiresDestruction && Dest.isIgnored());
Address RetAddr = Address::invalid();
- RawAddress RetAllocaAddr = RawAddress::invalid();
EHScopeStack::stable_iterator LifetimeEndBlock;
llvm
@@ -5158,14 +5155,17 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
} else if (!ReturnValue.isNull()) {
SRetPtr = ReturnValue.getAddress();
} else {
- SRetPtr = CreateMemTemp(RetTy, "tmp", &SRetAlloca);
+ SRetPtr = CreateMemTempWith
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
https://github.com/AlexVlx commented:
Gentle ping.
https://github.com/llvm/llvm-project/pull/114062
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>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/10] `sret` args should always point to the `alloca` AS, so
we ca
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/116804
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>From 02a607446bf23781255f401d880b67c705cf11fd Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 13:42:54 +
Subject: [PATCH 1/3] Use `used`'s element type if it's available.
---
llvm/lib/Bit
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116804
>From 02a607446bf23781255f401d880b67c705cf11fd Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 13:42:54 +
Subject: [PATCH 1/3] Use `used`'s element type if it's available.
---
llvm/lib/Bit
https://github.com/AlexVlx commented:
> Mind adding a test case? Perhaps something like the embed-bitcode.ll, but
> instead checking the round-tripping of compiler.used ?
Done, although slightly differently; it does reflect that when there is a
pre-existing compiler.used its element type is
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>From 02a607446bf23781255f401d880b67c705cf11fd Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 13:42:54 +
Subject: [PATCH 1/2] Use `used`'s element type if it's available.
---
llvm/lib/Bit
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116820
>From c5efdd24c0c889e26e3b00865780970ca5ed1f4c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 14:55:25 +
Subject: [PATCH 1/2] Translate `amdgpu_flat_work_group_size` into
`reqd_work_group_
https://github.com/AlexVlx closed
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AlexVlx wrote:
> > > reqd_work_group_size is for OpenCL reqd_work_group_size attribute and it
> > > sets exact block size. amdgpu-flat-work-group-size sets a (min, max)
> > > range for block size.
> > > HIP launch bounds sets a block size range (1, bound). It cannot be
> > > represented by req
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/116820
HIPAMD relies on the `amdgpu_flat_work_group_size` attribute to implement key
functionality such as the `__launch_bounds__` `__global__` function annotation.
This attribute is not available / directly translata
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/10] `sret` args should always point to the `alloca` AS, so
we ca
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/114481
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https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/11] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
@@ -5390,11 +5390,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
V->getType()->isIntegerTy())
V = Builder.CreateZExt(V, ArgInfo.getCoerceToType());
-// If the argument doesn't match, perform a bitcast to coerce it. This
-
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/10] `sret` args should always point to the `alloca` AS, so
we ca
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 1/9] `sret` args should always point to the `alloca` AS, so we
can
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/114062
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@@ -5159,16 +5156,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
} else if (!ReturnValue.isNull()) {
SRetPtr = ReturnValue.getAddress();
} else {
- SRetPtr = CreateMemTemp(RetTy, "tmp", &SRetAlloca);
+ SRetPtr = CreateMemTempWith
@@ -5390,11 +5390,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
V->getType()->isIntegerTy())
V = Builder.CreateZExt(V, ArgInfo.getCoerceToType());
-// If the argument doesn't match, perform a bitcast to coerce it. This
-
AlexVlx wrote:
> I could see only applying these rules to the target specific (i.e.
> non-language AS's) so `AS(3) *` would convert to `*` but not `__shared__ *`.
> The above example doesn't work because we consider `cuda_shared` and `AS(3)`
> distinct even though they lower to the same thing
AlexVlx wrote:
Gentle ping - I'd like to progress this in one form or another (target hook or
extending indirect to carry an AS). If there are other ideas / strong
preferences / over-my-dead-body objections, they'd be more than welcome.
https://github.com/llvm/llvm-project/pull/114062
AlexVlx wrote:
> For AMDGPU and NVPTX, pointers are allowed to drop their address spaces
> transparently. So, `void AS(3) *` can convert to `void *`. Languages like
> CUDA and SYCL and HIP use these 'language' address spaces to describe exactly
> this, but my assertion is that it's more of a f
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 1/8] `sret` args should always point to the `alloca` AS, so we
can
https://github.com/AlexVlx approved this pull request.
LGTM, thanks.
https://github.com/llvm/llvm-project/pull/112849
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https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 1/8] `sret` args should always point to the `alloca` AS, so we
can
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
@@ -6,48 +7,78 @@
; RUN: opt -O3 -S < %s | FileCheck -check-prefix=OPT %s
; RUN: opt -mtriple=amdgcn-- -O3 -S < %s | FileCheck -check-prefix=OPT %s
-; RUN: opt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck
-check-prefix=OPT %s
-; RUN: opt -mtriple=amdgcn--
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/114481
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https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
@@ -1780,6 +1780,14 @@ class TargetInfo : public TransferrableTargetInfo,
return 0;
}
+ /// \returns Target specific address space for indirect (e.g. sret)
arguments.
+ /// If such an address space exists, it must be convertible to and from the
+ /// alloca address s
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 1/9] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placehol
AlexVlx wrote:
> The following also currently crashes with the flags in question:
>
> ```
> void use_of_private_var()
> {
> int x = 0 ;
> __private void* xx = &x;
> }
> ```
>
> And the AST for the call in your testcase looks fine:
>
> ```
> `-CallExpr 0xd4aeec8 'void'
> |-Im
AlexVlx wrote:
> Don't know how anything was working before. There must have been a recent
> regression, but I haven't looked yet.
I don’t know if we want to do this blindly, it’s generally a good catch for
actual bugs. I assume that this “worked” before because the AS map hack was in
place.
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/110695
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 1/5] `sret` args should always point to the `alloca` AS, so we
can
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/113509
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 1/5] `sret` args should always point to the `alloca` AS, so we
can
@@ -6,48 +7,78 @@
; RUN: opt -O3 -S < %s | FileCheck -check-prefix=OPT %s
; RUN: opt -mtriple=amdgcn-- -O3 -S < %s | FileCheck -check-prefix=OPT %s
-; RUN: opt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck
-check-prefix=OPT %s
-; RUN: opt -mtriple=amdgcn--
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 1/9] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placehol
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/114481
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@@ -1024,6 +1024,16 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 1/8] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placehol
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 1/7] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placehol
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