ojhunt wrote:
> I think we should make a point of implementing this for address-discriminated
> `__ptrauth` qualifiers before we release it, because changing the type trait
> in a future release will be an ABI break.
I had been talking to @cor3ntin and decided we could do it later as this is a
@@ -2625,6 +2625,11 @@ void tools::AddStaticDeviceLibs(Compilation *C, const
Tool *T,
llvm::opt::ArgStringList &CC1Args,
StringRef Arch, StringRef Target,
bool isBitCodeSDL) {
+
+
https://github.com/kadircet approved this pull request.
thanks for the quick fix!
https://github.com/llvm/llvm-project/pull/144428
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@@ -117,6 +117,7 @@ get_property(LINK_LIBS GLOBAL PROPERTY
CLANG_UNITTEST_LINK_LIBS)
get_property(LLVM_COMPONENTS GLOBAL PROPERTY CLANG_UNITTEST_LLVM_COMPONENTS)
add_distinct_clang_unittest(AllClangUnitTests
${SRCS}
+ AllClangUnitTests.cpp
kadircet wrote:
vbvictor wrote:
Rebased + ping @PiotrZSL.
I'd merge it at the end of the month if there would be no more reviews.
https://github.com/llvm/llvm-project/pull/126434
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https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/144640
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quic-garvgupt wrote:
> > Do the fuchsia builders actually produce output on a failure? We seem to
> > just get exit code 1, but no indication of what filecheck had problems with.
>
> They do; here's a link! Let me know if you have an problems with the Web UI;
> I can paste things here if so.
https://github.com/vbvictor updated
https://github.com/llvm/llvm-project/pull/126434
>From 81a21a90e03e4b9cea58d6bcffddf3bde0f82710 Mon Sep 17 00:00:00 2001
From: Victor Baranov
Date: Mon, 3 Mar 2025 09:25:03 +0300
Subject: [PATCH 01/12] [clang-tidy] add scoped-lock-check
---
.../clang-tidy/m
https://github.com/amitamd7 converted_to_draft
https://github.com/llvm/llvm-project/pull/144635
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https://github.com/llvm/llvm-project/pull/144274
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https://github.com/pvelesko updated
https://github.com/llvm/llvm-project/pull/136412
>From fe6a426fc135c7232650b5ebac465ceaa66d7a20 Mon Sep 17 00:00:00 2001
From: Paulius Velesko
Date: Sat, 19 Apr 2025 10:02:59 +0300
Subject: [PATCH 1/3] HIPSPV: Unbundle SDL
This fixes the issue of rdc linking
https://github.com/vbvictor updated
https://github.com/llvm/llvm-project/pull/144274
>From 98fc81696400be2ea990d867375530ef3f544b82 Mon Sep 17 00:00:00 2001
From: Victor Baranov
Date: Sun, 15 Jun 2025 22:20:54 +0300
Subject: [PATCH 1/3] [Clang] Fix '-Wformat-overflow' FP when floats had
field-
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Garvit Gupta (quic-garvgupt)
Changes
This patch introduces enhancements to the Baremetal toolchain to support
GCC toolchain detection.
- If the --gcc-install-dir or --gcc-toolchain options are provided and
point to valid paths, the s
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/144640
This patch introduces enhancements to the Baremetal toolchain to support
GCC toolchain detection.
- If the --gcc-install-dir or --gcc-toolchain options are provided and
point to valid paths, the sysroot is
https://github.com/vbvictor edited
https://github.com/llvm/llvm-project/pull/144274
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@@ -43,6 +43,11 @@ void call_snprintf(double d, int n, int *ptr) {
__builtin_snprintf(node_name, sizeof(node_name), "%pOFn", ptr); //
nonkprintf-warning {{'snprintf' will always be truncated; specified size is 6,
but format string expands to at least 7}}
__builtin_snprintf
tclin914 wrote:
I've summarized the issue in
[#144639](https://github.com/llvm/llvm-project/issues/144639).
https://github.com/llvm/llvm-project/pull/144402
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@@ -683,6 +683,30 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32: {
+llvm::Type *RetTy = llvm::Type::getFloatTy(Builder.getContext());
+
@@ -635,5 +635,10 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi",
"nc", "bitop3-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc",
"f32-to-f16bf16-cvt-sr-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc",
"f32-to-
@@ -683,6 +683,30 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32: {
+llvm::Type *RetTy = llvm::Type::getFloatTy(Builder.getContext());
+
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown %s -emit-llvm -o - |
FileCheck %s
ranapratap55 wrote:
done.
https://github.com/llvm/llvm-pr
@@ -683,6 +683,30 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32: {
+llvm::Type *RetTy = llvm::Type::getFloatTy(Builder.getContext());
+
@@ -635,5 +635,10 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi",
"nc", "bitop3-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc",
"f32-to-f16bf16-cvt-sr-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc",
"f32-to-
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown %s -emit-llvm -o - |
FileCheck %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64:enable
+
+typedef int v8i __attribut
@@ -683,6 +683,30 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32: {
+llvm::Type *RetTy = llvm::Type::getFloatTy(Builder.getContext());
+
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown %s -emit-llvm -o - |
FileCheck %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64:enable
+
+typedef int v8i __attribut
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown %s -emit-llvm -o - |
FileCheck %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64:enable
+
+typedef int v8i __attribut
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown %s -emit-llvm -o - |
FileCheck %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64:enable
ranapratap55
https://github.com/ranapratap55 updated
https://github.com/llvm/llvm-project/pull/140210
>From d1571dd53f157c9d4180c51e709d9bed0ba00136 Mon Sep 17 00:00:00 2001
From: ranapratap55
Date: Fri, 16 May 2025 12:50:09 +0530
Subject: [PATCH 1/2] [WIP][AMDGPU] Support for type inferring image load/stor
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Amit Tiwari (amitamd7)
Changes
This patch handles the strided update in the `#pragma omp target update
from(data[a:b:c])` directive where 'c' represents the strided access leading to
non-contiguous update in the `data` array when the offl
@@ -4467,17 +4467,25 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
GlobalDecl GD, unsigned BuiltinID,
case Builtin::BI__builtin_trivially_relocate:
case Builtin::BImemmove:
case Builtin::BI__builtin_memmove: {
+QualType CopiedType = E->getArg(0)->getType()->getPoi
https://github.com/amitamd7 created
https://github.com/llvm/llvm-project/pull/144635
This patch handles the strided update in the `#pragma omp target update
from(data[a:b:c])` directive where 'c' represents the strided access leading to
non-contiguous update in the `data` array when the offloa
github-actions[bot] wrote:
Thank you for submitting a Pull Request (PR) to the LLVM Project!
This PR will be automatically labeled and the relevant teams will be notified.
If you wish to, you can add reviewers by using the "Reviewers" section on this
page.
If this is not working for you, it
@@ -520,6 +520,9 @@ def warn_drv_math_errno_enabled_after_veclib: Warning<
"math errno enabled by '%0' after it was implicitly disabled by '%1',"
" this may limit the utilization of the vector library">,
InGroup;
+def warn_drv_gcc_incompatible_complex_range_override: Warn
@@ -4467,17 +4467,25 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
GlobalDecl GD, unsigned BuiltinID,
case Builtin::BI__builtin_trivially_relocate:
case Builtin::BImemmove:
case Builtin::BI__builtin_memmove: {
+QualType CopiedType = E->getArg(0)->getType()->getPoi
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `clang-arm64-windows-msvc`
running on `linaro-armv8-windows-msvc-04` while building `clang` at step 6
"test-build-unified-tree-check-all".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/161/builds/6612
scout-zeng wrote:
@efriedma-quic Hi Eli, if there is any problem, please let me know.
https://github.com/llvm/llvm-project/pull/144625
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llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (scout-zeng)
Changes
`FORCE_INLINE __m128i _mm_sll_epi64(__m128i a, __m128i count)
{
long long c = count.vect_s64[0];
const int mc = c;
__m128i result_m128i;
if (likely(c >= 0 && c < 64)) {
result_m128i.vect_s64
github-actions[bot] wrote:
Thank you for submitting a Pull Request (PR) to the LLVM Project!
This PR will be automatically labeled and the relevant teams will be notified.
If you wish to, you can add reviewers by using the "Reviewers" section on this
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If this is not working for you, it
https://github.com/scout-zeng created
https://github.com/llvm/llvm-project/pull/144625
`FORCE_INLINE __m128i _mm_sll_epi64(__m128i a, __m128i count)
{
long long c = count.vect_s64[0];
const int mc = c;
__m128i result_m128i;
if (likely(c >= 0 && c < 64)) {
result_m128i.vec
https://github.com/rjmccall approved this pull request.
Thanks, LGTM.
https://github.com/llvm/llvm-project/pull/144458
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llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `arc-builder` running on
`arc-worker` while building `clang,llvm` at step 6
"test-build-unified-tree-check-all".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/3/builds/17667
Here is the relevant pie
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/144320
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Author: Jim Lin
Date: 2025-06-18T09:17:46+08:00
New Revision: 8ddada41df0488358373cff1d31a47e5ef4961e0
URL:
https://github.com/llvm/llvm-project/commit/8ddada41df0488358373cff1d31a47e5ef4961e0
DIFF:
https://github.com/llvm/llvm-project/commit/8ddada41df0488358373cff1d31a47e5ef4961e0.diff
LOG:
https://github.com/ahatanak updated
https://github.com/llvm/llvm-project/pull/144458
>From 180213a360c7b25784f84ada7112b30ee0bd1212 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka
Date: Fri, 13 Jun 2025 15:01:26 -0700
Subject: [PATCH 1/5] [Sema][ObjC] Loosen restrictions on reinterpret_cast
invo
andrurogerz wrote:
> I think that the clang semantics are technically correct
Yes, agreed. And in case it wasn't clear, this is `clang` behavior and is not
specific to `clang-cl`.
https://github.com/llvm/llvm-project/pull/144386
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llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: None (Pavithra029)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/144622.diff
1 Files Affected:
- (modified) clang/lib/CodeGen/CodeGenModule.cpp (+100)
``diff
diff --git a/clang/lib/CodeGen/CodeGenM
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (Pavithra029)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/144622.diff
1 Files Affected:
- (modified) clang/lib/CodeGen/CodeGenModule.cpp (+100)
``diff
diff --git a/clang/lib/CodeGen/CodeGenModule.cp
github-actions[bot] wrote:
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None
>From d41ac68039e6d654249fbeceb3b77c4b6780f9c0 Mon Sep 17 00:00:00 2001
From: pavithra
Date: Wed, 18 Jun 2025 05:50:13 +0530
Subject: [PATCH] Inject compilation command into __cli_ global variable
---
https://github.com/andykaylor approved this pull request.
https://github.com/llvm/llvm-project/pull/144376
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https://github.com/compnerd closed
https://github.com/llvm/llvm-project/pull/144386
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Author: Andrew Rogers
Date: 2025-06-17T17:21:40-07:00
New Revision: abbdd1670d8b12dd72ec353b14e256619ff4694b
URL:
https://github.com/llvm/llvm-project/commit/abbdd1670d8b12dd72ec353b14e256619ff4694b
DIFF:
https://github.com/llvm/llvm-project/commit/abbdd1670d8b12dd72ec353b14e256619ff4694b.diff
https://github.com/compnerd approved this pull request.
It is odd to me that this works with `cl`, I think that the clang semantics are
technically correct. But, when in Rome
https://github.com/llvm/llvm-project/pull/144386
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efriedma-quic wrote:
For the constant expression handling stuff, I think you have the basic
framework working correctly; if we run into additional issues, I'm happy to
leave handling them for followups.
https://github.com/llvm/llvm-project/pull/138972
__
@@ -0,0 +1,38 @@
+; This tests directly annotating a function with
marked_for_windows_hot_patching.
+;
+; RUN: llc -mtriple=x86_64-windows < %s | FileCheck %s
efriedma-quic wrote:
If you put the tests in test/CodeGen/Generic, the test runner will try to run
the
@@ -0,0 +1,21 @@
+// This verifies that hotpatch function attributes are correctly propagated
when compiling directly to OBJ.
+//
+// RUN: echo this_gets_hotpatched > %t.patch-functions.txt
+// RUN: %clang_cl -c --target=x86_64-windows-msvc -O2 /Z7
-fms-secure-hotpatch-functions
@@ -389,6 +389,17 @@ def CoroDestroyOnlyWhenComplete :
EnumAttr<"coro_only_destroy_when_complete", In
/// pipeline to perform elide on the call or invoke instruction.
def CoroElideSafe : EnumAttr<"coro_elide_safe", IntersectPreserve, [FnAttr]>;
+/// Function is marked for Win
@@ -219,6 +219,11 @@ Changes in existing checks
tolerating fix-it breaking compilation when functions is used as pointers
to avoid matching usage of functions within the current compilation unit.
+- Improved :doc: `bugprone-sizeof-expression
+ ` check.
+ Introduced WarnOnS
https://github.com/malavikasamak updated
https://github.com/llvm/llvm-project/pull/143205
>From 52e4413ea1e701dfe0b24cf957a26bb72732f066 Mon Sep 17 00:00:00 2001
From: MalavikaSamak
Date: Wed, 21 May 2025 16:06:44 -0700
Subject: [PATCH 1/6] Place holder message for sizeof operator in loops.
--
https://github.com/rjmccall commented:
Could you also test that casts which preserve qualifiers work as expected?
https://github.com/llvm/llvm-project/pull/144458
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@@ -126,6 +130,36 @@ _LIBUNWIND_HIDDEN int __unw_set_reg(unw_cursor_t *cursor,
unw_regnum_t regNum,
// First, get the FDE for the old location and then update it.
co->getInfo(&info);
co->setInfoBasedOnIPRegister(false);
+
+#if __has_feature(ptrauth_calls)
+
@@ -1877,6 +1946,32 @@ inline Registers_arm64::Registers_arm64(const void
*registers) {
memcpy(_vectorHalfRegisters,
static_cast(registers) + sizeof(GPRs),
sizeof(_vectorHalfRegisters));
+#if __has_feature(ptrauth_calls)
kovdan01 wrote:
It
@@ -83,7 +83,13 @@ __llvm_profile_iterate_data(const __llvm_profile_data *Data)
{
/* This method is only used in value profiler mock testing. */
COMPILER_RT_VISIBILITY void *
__llvm_get_function_addr(const __llvm_profile_data *Data) {
- return Data->FunctionPointer;
+ void
@@ -1845,10 +1871,53 @@ class _LIBUNWIND_HIDDEN Registers_arm64 {
uint64_t getSP() const { return _registers.__sp; }
void setSP(uint64_t value) { _registers.__sp = value; }
- uint64_t getIP() const { return _registers.__pc; }
- void setIP(uint
@@ -1845,10 +1871,53 @@ class _LIBUNWIND_HIDDEN Registers_arm64 {
uint64_t getSP() const { return _registers.__sp; }
void setSP(uint64_t value) { _registers.__sp = value; }
- uint64_t getIP() const { return _registers.__pc; }
- void setIP(uint
@@ -83,7 +83,13 @@ __llvm_profile_iterate_data(const __llvm_profile_data *Data)
{
/* This method is only used in value profiler mock testing. */
COMPILER_RT_VISIBILITY void *
__llvm_get_function_addr(const __llvm_profile_data *Data) {
- return Data->FunctionPointer;
+ void
@@ -93,6 +98,13 @@ class _LIBUNWIND_HIDDEN Registers_x86 {
uint32_t getEDI() const { return _registers.__edi; }
void setEDI(uint32_t value) { _registers.__edi = value; }
+ typedef uint32_t reg_t;
+ typedef uint32_t link_reg_t;
+ void loadAndAuthenticateLin
@@ -1845,10 +1871,53 @@ class _LIBUNWIND_HIDDEN Registers_arm64 {
uint64_t getSP() const { return _registers.__sp; }
void setSP(uint64_t value) { _registers.__sp = value; }
- uint64_t getIP() const { return _registers.__pc; }
- void setIP(uint
@@ -1877,6 +1946,32 @@ inline Registers_arm64::Registers_arm64(const void
*registers) {
memcpy(_vectorHalfRegisters,
static_cast(registers) + sizeof(GPRs),
sizeof(_vectorHalfRegisters));
+#if __has_feature(ptrauth_calls)
+ uint64_t pcRegister = 0;
+ memcp
https://github.com/rnk updated https://github.com/llvm/llvm-project/pull/144428
>From afb050103754e6b4656c68da8ddfb6b1a4e03e5d Mon Sep 17 00:00:00 2001
From: Reid Kleckner
Date: Mon, 16 Jun 2025 20:08:12 +
Subject: [PATCH 1/4] [clang] Register all LLVM targets in AllClangUnitTest
main
Addr
https://github.com/efriedma-quic closed
https://github.com/llvm/llvm-project/pull/142713
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Author: Eli Friedman
Date: 2025-06-17T16:43:55-07:00
New Revision: f2d2c99866dfd133e7b9c98b1d4983c6bce33d67
URL:
https://github.com/llvm/llvm-project/commit/f2d2c99866dfd133e7b9c98b1d4983c6bce33d67
DIFF:
https://github.com/llvm/llvm-project/commit/f2d2c99866dfd133e7b9c98b1d4983c6bce33d67.diff
https://github.com/a-tarasyuk edited
https://github.com/llvm/llvm-project/pull/144619
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arsenm wrote:
> and that's why you want to have single element loads that get inserted into a
> vector and then perform sub-vector extracts on it?
We care about eliminate stack usage at any cost. Big load are always better,
even if not naturally aligned. When we do care about alignment, we onl
arsenm wrote:
> We do support unaligned access IIUC, and it is actually required by HSA ABI.
> CC @arsenm
Unaligned access has been supported since almost always. There's just a mode
control for it, you can disable it in the driver though
https://github.com/llvm/llvm-project/pull/133301
__
https://github.com/rnk updated https://github.com/llvm/llvm-project/pull/144428
>From afb050103754e6b4656c68da8ddfb6b1a4e03e5d Mon Sep 17 00:00:00 2001
From: Reid Kleckner
Date: Mon, 16 Jun 2025 20:08:12 +
Subject: [PATCH 1/3] [clang] Register all LLVM targets in AllClangUnitTest
main
Addr
https://github.com/rnk edited https://github.com/llvm/llvm-project/pull/144428
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@@ -0,0 +1,24 @@
+//===- clang/unittests/AllClangUnitTests.cpp
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -117,6 +117,7 @@ get_property(LINK_LIBS GLOBAL PROPERTY
CLANG_UNITTEST_LINK_LIBS)
get_property(LLVM_COMPONENTS GLOBAL PROPERTY CLANG_UNITTEST_LLVM_COMPONENTS)
add_distinct_clang_unittest(AllClangUnitTests
${SRCS}
+ AllClangUnitTests.cpp
rnk wrote:
I spo
https://github.com/evelez7 edited
https://github.com/llvm/llvm-project/pull/144617
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evelez7 wrote:
* **#144617** https://app.graphite.dev/github/pr/llvm/llvm-project/144617?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/1446
https://github.com/evelez7 created
https://github.com/llvm/llvm-project/pull/144617
None
>From bd5747e542e23078a98a830da191e5f1f72bd85b Mon Sep 17 00:00:00 2001
From: Erick Velez
Date: Tue, 17 Jun 2025 15:11:02 -0700
Subject: [PATCH] [clang-doc] mangle specialization file names
---
clang-too
@@ -0,0 +1,24 @@
+//===- clang/unittests/AllClangUnitTests.cpp
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/zygoloid approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/142713
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efriedma-quic wrote:
Ping
https://github.com/llvm/llvm-project/pull/142713
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lenary wrote:
Nice, I can navigate that UI.
Looks like a similar thing that I fixed-forward, but this time with a different
unwind library, but clang isn't very happy with mixing unwind libraries anyway.
I think I'll leave this to @quic-garvgupt to fix, using the info from your link.
https://
@@ -80,12 +80,19 @@ unsigned
CodeGenTypes::ClangCallConvToLLVMCallConv(CallingConv CC) {
return llvm::CallingConv::AArch64_VectorCall;
case CC_AArch64SVEPCS:
return llvm::CallingConv::AArch64_SVE_VectorCall;
- case CC_AMDGPUKernelCall:
-return llvm::CallingConv:
mysterymath wrote:
> Do the fuchsia builders actually produce output on a failure? We seem to just
> get exit code 1, but no indication of what filecheck had problems with.
They do; here's a link! Let me know if you have an problems with the Web UI; I
can paste things here if so.
https://luci-
lenary wrote:
We probably need to file an infrastructure ticket to get to the bottom of this
issue. I've seen the same issues @mshockwave has seen.
https://github.com/llvm/llvm-project/pull/144402
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lenary wrote:
Do the fuchsia builders actually produce output on a failure? We seem to just
get exit code 1, but no indication of what filecheck had problems with.
https://github.com/llvm/llvm-project/pull/121829
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shiltian wrote:
> I assume AMDGPU does not support unaligned loads
We do support unaligned access IIUC, and it is actually required by HSA ABI. CC
@arsenm
https://github.com/llvm/llvm-project/pull/133301
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https://github.com/efriedma-quic closed
https://github.com/llvm/llvm-project/pull/144407
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Author: Eli Friedman
Date: 2025-06-17T15:27:41-07:00
New Revision: 3f33c8482fc0b8dd0d2596262ebd0ed73d41665d
URL:
https://github.com/llvm/llvm-project/commit/3f33c8482fc0b8dd0d2596262ebd0ed73d41665d
DIFF:
https://github.com/llvm/llvm-project/commit/3f33c8482fc0b8dd0d2596262ebd0ed73d41665d.diff
nikic wrote:
On x86, what we actually end up doing is to combine those to unaligned i64
loads (see https://godbolt.org/z/P5z674x4r), which is probably the best outcome
if they are supported. I assume AMDGPU does not support unaligned loads, and
that's why you want to have single element loads
https://github.com/PiJoules created
https://github.com/llvm/llvm-project/pull/144612
This saves about 3kB on embedded project.
>From 9f179e644ddadba15f51d45479b20744b66f6291 Mon Sep 17 00:00:00 2001
From: Leonard Chan
Date: Tue, 17 Jun 2025 15:06:10 -0700
Subject: [PATCH] [WIP][llvm] Flag to f
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Eli Friedman (efriedma-quic)
Changes
This is similar to -msve-vector-bits, but for streaming mode: it constrains the
legal values of "vscale", allowing optimizations based on that constraint.
This also fixes conversions between
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
@llvm/pr-subscribers-backend-arm
Author: Eli Friedman (efriedma-quic)
Changes
This is similar to -msve-vector-bits, but for streaming mode: it constrains the
legal values of "vscale", allowing optimizations based on that constraint.
This a
https://github.com/efriedma-quic created
https://github.com/llvm/llvm-project/pull/144611
This is similar to -msve-vector-bits, but for streaming mode: it constrains the
legal values of "vscale", allowing optimizations based on that constraint.
This also fixes conversions between SVE vectors a
rjmccall wrote:
I've been informed that I've misunderstood the nature of "trivial relocation" —
it is not a "trivial" operation in the usual sense of triviality, it's just an
operation that (1) can be done primitively by the compiler and (2) cannot fail.
That addresses my concern, because we c
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