kernel build fails if DIAGNOSTIC option is undefined

2020-01-18 Thread Andrius V
ntf(i == state ? " %02x |" : " %02x", sc->packet[i]); } +#endif Regards, Andrius V

Incorrect RCSID value in /distrib/notes/octeon/xfer file

2020-02-16 Thread Andrius V
@@ -dnl$OpenBS$ +dnl$OpenBSD$ Installation is supported from several media types, including: FFS partitions Regards, Andrius V

Re: vte(4): restore MDC clock speed register value after MAC reset

2021-12-09 Thread Andrius V
Regards, Andrius V On Mon, Sep 13, 2021 at 1:42 PM Andrius V wrote: > > Hi, > > On some Vortex86 SoCs MDC speed control register needs to be restored > to original value after MAC reset. This issue happens if MAC has non > default VTE_MDCSC register value before reset, and

Re: vte(4): restore MDC clock speed register value after MAC reset

2022-03-23 Thread Andrius V
needed for at least Vortex86DX3 machines (since reset changes register value to MDCSC_DEFAULT value, which may not be the original value, thus causing some phy registers read failures). Attaching updated patch for current sources. Thank you! Regards, Andrius V On Fri, Dec 10, 2021 at 12:21 AM Andrius

Re: vte(4): restore MDC clock speed register value after MAC reset

2022-04-19 Thread Andrius V
vision is below 4 (however, I haven't updated my code to current yet). Regards, Andrius V On Tue, Apr 19, 2022 at 6:29 AM Kevin Lo wrote: > > Hi Andrius, > > I finally have hardware (DMP EB-3360-C2CF) to verify your diff and confirm > that restoring VTE_MDCSC value to original

Re: vte(4): restore MDC clock speed register value after MAC reset

2022-04-20 Thread Andrius V
I root hub" rev 1.00/1.00 addr 1 vscsi0 at root scsibus1 at vscsi0: 256 targets softraid0 at root scsibus2 at softraid0: 256 targets root on wd0a (52c91035a45ce8fc.a) swap on wd0b dump on wd0b Thank you. Regards, Andrius V On Wed, Apr 20, 2022 at 5:37 AM Kevin Lo wrote: > > On Tue, Ap

aq* on i386

2022-06-26 Thread Andrius V
reasons, since the difference is tangible). In these cases, I can't use Aquantia card and need either to attach supported card or compile a new kernel. Regards, Andrius V

Re: aq* on i386

2022-06-26 Thread Andrius V
, Mike Larkin wrote: > > On Sun, Jun 26, 2022 at 01:26:28PM +0300, Andrius V wrote: > > > Hi, > > > > > > Is it possible to add aq* to i386 kernel configuration by default? The > > > driver seems to work out of the box, at least on my AQC100 SFP+ based > &

Typo in if_bge.c

2024-02-10 Thread Andrius V
Multiple typos were fixed in this file in the past, but one slipped away. diff --git a/sys/dev/pci/if_bge.c b/sys/dev/pci/if_bge.c index 8dc020150c7..4ad031a5ec9 100644 --- a/sys/dev/pci/if_bge.c +++ b/sys/dev/pci/if_bge.c @@ -2099,7 +2099,7 @@ bge_blockinit(struct bge_softc *sc) * The BD

Please add model 5 and 6 to rdcphy(4)

2021-09-07 Thread Andrius V
II_OUI_RDC, MII_MODEL_RDC_R6040_2, + MII_STR_RDC_R6040_2 }, + { MII_OUI_RDC, MII_MODEL_RDC_R6040_3, + MII_STR_RDC_R6040_3 }, { 0,0, NULL }, }; Regards, Andrius V

vte(4): restore MDC clock speed register value after MAC reset

2021-09-13 Thread Andrius V
!= MDCSC_DEFAULT) +CSR_WRITE_2(sc, VTE_MDCSC, mdcsc); } int Regards, Andrius V

incorrect RCS ID headers

2025-05-18 Thread Andrius V
ing closing $ usr.sbin/sysupgrade/Makefile extra space before closing $ Regards, Andrius V