Applied, thanks!
Damien Zammit via Bug reports for the GNU Hurd, le lun. 09 déc. 2024 12:17:53
+, a ecrit:
> Since modern x86 cpus only support 4 bits of destination field
> in ICR, we could only address up to 16 processors, assuming
> their physical APIC ID was < 0x10. Some processors eg AM
Since modern x86 cpus only support 4 bits of destination field
in ICR, we could only address up to 16 processors, assuming
their physical APIC ID was < 0x10. Some processors eg AMD fam15h
have physical apic ids starting at 0x10 but only support 4 bits.
So these lapics are unaddressable using physi
