Re: [PATCH] gnumach - Restrict pci io cfg ports to one process

2018-12-05 Thread Samuel Thibault
Damien Zammit, le dim. 11 nov. 2018 13:24:00 +1100, a ecrit: > On 11/11/18 12:51, Samuel Thibault wrote: > > Damien Zammit, le dim. 11 nov. 2018 12:43:07 +1100, a ecrit: > >> +#define IS_IN_PROTECTED_RANGE(from, to) \ > >> + ( ( ( from <= PCI_CFG1_START ) && ( to >= PCI_CFG1_END ) ) || \ > > > >

Re: [PATCH] gnumach - Restrict pci io cfg ports to one process

2018-11-10 Thread Damien Zammit
On 11/11/18 12:51, Samuel Thibault wrote: > Damien Zammit, le dim. 11 nov. 2018 12:43:07 +1100, a ecrit: >> +#define IS_IN_PROTECTED_RANGE(from, to) \ >> + ( ( ( from <= PCI_CFG1_START ) && ( to >= PCI_CFG1_END ) ) || \ > > That should be from <= END && to >= BEGIN, shouldn't it? Well, in my min

Re: [PATCH] gnumach - Restrict pci io cfg ports to one process

2018-11-10 Thread Samuel Thibault
Damien Zammit, le dim. 11 nov. 2018 12:43:07 +1100, a ecrit: > +#define IS_IN_PROTECTED_RANGE(from, to) \ > + ( ( ( from <= PCI_CFG1_START ) && ( to >= PCI_CFG1_END ) ) || \ That should be from <= END && to >= BEGIN, shouldn't it? Samuel

Re: [PATCH] gnumach - Restrict pci io cfg ports to one process

2018-11-10 Thread Damien Zammit
On 10/11/18 20:50, Samuel Thibault wrote: > The data register port is 0xCFC + (reg & 3); so it could be as much as > 0xCFF. > > The x86 conf2 method also uses 0xC000 | dev << 8 | reg; so we need to > also protect 0xc000 - 0xcfff. See attached patch with corrections. Thanks, Damien >From b79f52db

Re: [PATCH] gnumach - Restrict pci io cfg ports to one process

2018-11-10 Thread Samuel Thibault
Again, thanks :) Damien Zammit, le sam. 10 nov. 2018 19:17:32 +1100, a ecrit: > @@ -185,6 +191,13 @@ i386_io_perm_create (const ipc_port_t master_port, > io_port_t from, io_port_t to, >if (from > to) > return KERN_INVALID_ARGUMENT; > > + if (from <= PCI_CFG1_ADDRESS_REG && to >= PCI_C

[PATCH] gnumach - Restrict pci io cfg ports to one process

2018-11-10 Thread Damien Zammit
Hi all, This patch for gnumach restricts the number of processes that can simultaneously access pci io cfg range of ports down to 1 as per discussion: https://lists.x.org/archives/xorg-devel/2018-November/057691.html Please review attached, thanks, Damien >From 8f5525e8d46b5cf47d7eaaeb92cdc2474