[PATCH v2 4/4 gnumach] smp: Fix INIT/STARTUP IPI sequence

To be fixed: Find a way to allocate memory below 1MiB. Otherwise, this hardcodes 0x3000 as the starting eip. TESTED: works in qemu TESTED: works hardware with AMD cpu --- i386/i386/mp_desc.c | 15 +++-- i386/i386/smp.c | 126 +--- i386/i386/smp.h

[PATCH v2 1/4 gnumach] separate lapic_enable from lapic_setup

This allows us to init the lapic without necessarily turning on the IOAPIC interrupts. --- i386/i386/apic.c | 15 +-- i386/i386/apic.h | 2 ++ i386/i386/mp_desc.c | 12 +--- i386/i386at/ioapic.c | 1 + 4 files changed, 25 insertions(+), 5 deletions(-) diff --git a/i

[PATCH v2 0/4 gnumach] SMP on AMD

Hi, Here are the changes from previous review. I did not make changes to ensure pit fallback because the pit one-shot code is broken; there is no point making it fall back to a delay that does not work. I tried fixing the pit code, but it resulted in strange behaviour. We can assume every x86

[PATCH v2 3/4 gnumach] smp: Use HPET instead of pit one-shot that is unreliable

NB: Assume every x86 board that uses ACPI has a HPET. We can roll back to PIT in the cases where its not present, but the PIT one shot code is currently broken. --- i386/i386/smp.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/i386/i386/smp.c b/i386/i386/smp.c index fb

[PATCH v2 2/4 gnumach] Add HPET timer for small accurate delays

TESTED: This works in qemu correctly TESTED: This works on an AMD board with ACPI v2.0 correctly --- i386/i386/apic.c | 97 +++ i386/i386/apic.h | 5 ++ i386/i386at/acpi_parse_apic.c | 35 ++--- i386/i386at/acpi_parse_apic.h | 23 +

Re: [PATCH 3/6 gnumach] smp: Remove hardcoded AP_BOOT_ADDR

Applied and fixed, thanks! Damien Zammit, le lun. 05 févr. 2024 11:33:49 +, a ecrit: > This took some time to figure out. > Involves a hand-crafted 16 bit assembly instruction [1] > because it requires an immediate for the memory address > of far jump. This required self-modifying code > to i

Re: [PATCH 6/6 gnumach] smp: Fix INIT/STARTUP IPI sequence

Hello, Damien Zammit, le lun. 05 févr. 2024 11:34:09 +, a ecrit: > Outstanding: Find a way to allocate memory below 1MiB. We could make the biosmem's biosmem_bootstrap_common code reserve the first physical page it finds from the multiboot mem map. > diff --git a/i386/i386/mp_desc.c b/i386/i

Re: [PATCH 5/6 gnumach] smp: Use HPET instead of pit one-shot that is unreliable

ditto. Damien Zammit, le lun. 05 févr. 2024 11:34:03 +, a ecrit: > NB: Every x86 board that uses ACPI most likely has a HPET. > We can roll back to PIT in the cases where its not present, > but the PIT one shot code is definitely currently broken. > --- > i386/i386/smp.c | 7 +++ > 1 file

Re: [PATCH 4/6 gnumach] Add HPET timer for small accurate delays

Hello, See my previous review on this one. Samuel Damien Zammit, le lun. 05 févr. 2024 11:33:56 +, a ecrit: > TESTED: This works in qemu correctly > TESTED: This works on an AMD board with ACPI v2.0 correctly > --- > i386/i386/apic.c | 87 +++ >

Re: [PATCH 2/6 gnumach] separate lapic_enable from lapic_setup

Hello, Damien Zammit, le lun. 05 févr. 2024 11:33:44 +, a ecrit: > @@ -312,12 +313,10 @@ start_other_cpus(void) > memcpy((void*)phystokv(AP_BOOT_ADDR), (void*) &apboot, > (uint32_t)&apbootend - (uint32_t)&apboot); > > -#ifndef APIC > - lapic_enable(); /* Enable lapic o

Re: [PATCH 1/6 gnumach] Fix apic_send_ipi function clobbering read only fields

Applied, thanks! Damien Zammit, le lun. 05 févr. 2024 11:33:39 +, a ecrit: > This was the root cause of failing to INIT. > We were clobbering remote_read_status. > And also, we need to reference the .r register > when writing the ICR regs otherwise I think > it writes all of the block. > --- >

[PATCH 5/6 gnumach] smp: Use HPET instead of pit one-shot that is unreliable

NB: Every x86 board that uses ACPI most likely has a HPET. We can roll back to PIT in the cases where its not present, but the PIT one shot code is definitely currently broken. --- i386/i386/smp.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/i386/i386/smp.c b/i386/i38

[PATCH 3/6 gnumach] smp: Remove hardcoded AP_BOOT_ADDR

This took some time to figure out. Involves a hand-crafted 16 bit assembly instruction [1] because it requires an immediate for the memory address of far jump. This required self-modifying code to inject the next instruction, therefore I added a near jump to clear the instruction cache queue in ca

[PATCH 2/6 gnumach] separate lapic_enable from lapic_setup

This allows us to init the lapic without necessarily turning on the IOAPIC interrupts. --- i386/i386/apic.c | 15 +-- i386/i386/apic.h | 2 ++ i386/i386/mp_desc.c | 6 +++--- i386/i386at/ioapic.c | 1 + 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/i386/i3

[PATCH 6/6 gnumach] smp: Fix INIT/STARTUP IPI sequence

Outstanding: Find a way to allocate memory below 1MiB. Otherwise, this hardcodes 0x3000 as the starting eip. TESTED: works in qemu TESTED: works hardware with AMD cpu --- i386/i386/mp_desc.c | 15 -- i386/i386/smp.c | 114 +--- i386/i386/smp.h

[PATCH 4/6 gnumach] Add HPET timer for small accurate delays

TESTED: This works in qemu correctly TESTED: This works on an AMD board with ACPI v2.0 correctly --- i386/i386/apic.c | 87 +++ i386/i386/apic.h | 4 ++ i386/i386at/acpi_parse_apic.c | 35 ++ i386/i386at/acpi_parse_apic.h | 23

[PATCH 0/6 gnumach] SMP on AMD hardware

Hi all, This patchset fixes a number of things wrong with smp and most of all fixes the root cause of an AP startup problem (Patch 1), which may also be affecting IPIs in general. In qemu with smp, I get a new panic after all modules are loaded: ../kern/slab.c:966: kmem_cache_alloc_from_slab: \

[PATCH 1/6 gnumach] Fix apic_send_ipi function clobbering read only fields

This was the root cause of failing to INIT. We were clobbering remote_read_status. And also, we need to reference the .r register when writing the ICR regs otherwise I think it writes all of the block. --- i386/i386/apic.c | 8 ++-- i386/i386/apic.h | 2 +- 2 files changed, 7 insertions(+), 3