[Bug gas/18625] Thumb2 branch out of range error

2015-07-09 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=18625 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug binutils/22464] New: x86 gas -n option does not work

2017-11-20 Thread wilson at gcc dot gnu.org
Assignee: unassigned at sourceware dot org Reporter: wilson at gcc dot gnu.org Target Milestone: --- I noticed this by accident. The x86 assembler has a -n option which says to emit one byte nops instead of multi-byte nops. But when I try it, it doesn't work. rohan:2162

[Bug binutils/22465] New: objcopy interleave fails if section address not multiple of interleave

2017-11-20 Thread wilson at gcc dot gnu.org
: normal Priority: P2 Component: binutils Assignee: unassigned at sourceware dot org Reporter: wilson at gcc dot gnu.org Target Milestone: --- Created attachment 10624 --> https://sourceware.org/bugzilla/attachment.cgi?id=10624&action=edit Proposed fix

[Bug binutils/22465] objcopy interleave fails if section address not multiple of interleave

2017-12-06 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22465 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug binutils/22465] objcopy interleave fails if section address not multiple of interleave

2017-12-06 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22465 Jim Wilson changed: What|Removed |Added Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org

[Bug gas/22599] [RISCV] fsrmi and fsflagsi pseudoinstructions aren't recognised

2017-12-13 Thread wilson at gcc dot gnu.org
||wilson at gcc dot gnu.org Resolution|--- |FIXED Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org --- Comment #2 from Jim Wilson --- Patch committed to mainline. -- You are receiving this mail because: You are on

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-08 Thread wilson at gcc dot gnu.org
||2018-01-08 CC||wilson at gcc dot gnu.org Ever confirmed|0 |1 -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-08 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 Jim Wilson changed: What|Removed |Added Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-08 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 --- Comment #2 from Jim Wilson --- Note that the testcase is trying to use absolute addresses with a pc-relative branch. The assembler can't know the address the linker will assign to the code, so this requires a relocation. I don't know if

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-08 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 --- Comment #4 from Jim Wilson --- I would expect this to work .option norelax beq s1, s0, .+102 bne a4, a5, .-4096 jal a2, 1048574 I get <.L0 >: 0: 06848363beq s1,s0,66 <.L0 +0

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-08 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 --- Comment #6 from Jim Wilson --- The address printed for jal is nonsense because it has a reloc, but the address for the branches should be correct. I think the problem with the is that we have two ".L0 " fake symbols, and objdump is using

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-09 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 --- Comment #8 from Jim Wilson --- Branches work the same way on RISC-V as they do on MIPS. Here is a mips example to show that. rohan:2123$ cat tmp.s _start: .skip 4096 beq $6, $7, 100 bne $4, $5, 4096 .skip

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-10 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 --- Comment #11 from Jim Wilson --- You must be careful when interpreting an unrelocated object file. The relocation 0: R_MIPS_PC16 *ABS* makes it clear that you have a zero-based absolute address in the branch. The disassembler is

[Bug ld/22756] Linker relaxation miscalculates symbol addresses on riscv

2018-01-29 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22756 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug ld/22756] Linker relaxation miscalculates symbol addresses on riscv

2018-02-02 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22756 Jim Wilson changed: What|Removed |Added Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org

[Bug ld/15904] ia64, ELF, 'Can't relax br (PCREL21B)' error message on --no-keep-memory

2018-02-26 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=15904 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug ld/15904] ia64, ELF, 'Can't relax br (PCREL21B)' error message on --no-keep-memory

2018-02-26 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=15904 --- Comment #3 from Jim Wilson --- The patch looks mostly correct, but we should be setting changed_contents also. The patch looks small enough and obvious enough that I don't think that we need a copyright assignment for the provided patch.

[Bug ld/15904] ia64, ELF, 'Can't relax br (PCREL21B)' error message on --no-keep-memory

2018-02-26 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=15904 --- Comment #5 from Jim Wilson --- Updated patch committed. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://li

[Bug ld/15904] ia64, ELF, 'Can't relax br (PCREL21B)' error message on --no-keep-memory

2018-02-26 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=15904 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/22903] [AArch64] Insufficient veneer stub alignment

2018-02-28 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22903 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug ld/22756] Linker relaxation miscalculates symbol addresses on riscv

2018-02-28 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22756 --- Comment #4 from Jim Wilson --- I found another problem with linker relaxation and symbol sizes. gamma05:2463$ cat tmp.c extern void sub3 (void); void __attribute__ ((noinline)) sub2 (void) { sub3 (); } void __attribute__ ((noinline))

[Bug ld/22903] [AArch64] Insufficient veneer stub alignment

2018-03-01 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22903 --- Comment #7 from Jim Wilson --- I don't particularly care how this gets fixed. Your patch seems to have a flaw. You are skipping over the first 4 bytes of the stub if it isn't aligned, but you aren't increasing the size of the stub to all

[Bug ld/22920] Segfault in ld with RISC-V binary target

2018-03-05 Thread wilson at gcc dot gnu.org
||2018-03-06 CC||wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- Your linker script sets the output format to binary. Unfortunately, the current RISC-V linker only works for ELF

[Bug ld/22920] Segfault in ld with RISC-V binary target

2018-03-06 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22920 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/22920] Segfault in ld with RISC-V binary target

2018-03-06 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22920 Jim Wilson changed: What|Removed |Added Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org

[Bug binutils/22941] binutils build fails if intl/plural.y is newer than intl/plural.c

2018-03-09 Thread wilson at gcc dot gnu.org
||2018-03-09 CC||wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- I just got the same bug report for a riscv* target. I can reproduce this failure for any target by forcing intl

[Bug ld/22945] ia64 ld testsuite fails on ld/testsuite/ld-elfvsb/elfvsb.exp

2018-03-09 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22945 --- Comment #1 from Jim Wilson --- I don't have any easy way to look at this. I don't have access to an ia64-linux machine. Ubuntu doesn't have an ia64-linux cross compiler. And the visibility tests are not run for ia64-elf. So I'd have to

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-03-14 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-03-14 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 --- Comment #3 from Jim Wilson --- I have a Fedora stage4 disk image that I'm running on qemu, and which has glibc-2.27. Libraries are in /usr/lib64 exactly as I expect. You pointed at part 0 of a 19 part patch set. I'm guessing you are tal

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-03-14 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 --- Comment #4 from Jim Wilson --- Note that gcc has #define STARTFILE_PREFIX_SPEC \ "/lib" XLEN_SPEC "/" ABI_SPEC "/ " \ "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ " \ "/lib/ "

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-03-14 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 --- Comment #5 from Jim Wilson --- I need more info. How was gcc configured? What are the options that gcc is passing to the linker? How are the libraries structured? What is in /usr/lib for instance. What OS and distro is this? If this

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-03-14 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 --- Comment #7 from Jim Wilson --- DJ Delorie provided some helpful info about Fedora RISC-V port in a chat and I'm now starting to understand the problem. Turns out that Fedora does put libraries in /usr/lib64/lp64d, and then puts links in /

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-03-14 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 --- Comment #8 from Jim Wilson --- If gcc is configured --enable-multilib, then it appears that you get the -L options you need for this to work. If gcc is configured --disable-multilib, then you do not get the -L options needed for this to w

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-03-15 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 --- Comment #11 from Jim Wilson --- (In reply to jos...@codesourcery.com from comment #10) > Again, the quoted error is about a search that uses -rpath-link paths but > *not* -L paths. GCC uses the right -L paths automatically, but > LIBPAT

[Bug binutils/22941] binutils build fails if intl/plural.y is newer than intl/plural.c

2018-04-05 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22941 --- Comment #3 from Jim Wilson --- There is no fix in the PR. The list of files is just showing that plural.c is the only bison output file in the git tree. The glibc solution is to drop the generated file from the git tree, and always gener

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-05-04 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 Jim Wilson changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-05-04 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22962 --- Comment #15 from Jim Wilson --- I've posted a proposed patch for review https://sourceware.org/ml/binutils/2018-05/msg00043.html And there is also a gcc part as it adds new linker emulations https://gcc.gnu.org/ml/gcc-patches/2018-

[Bug ld/22962] [RISCV] add abi subdirectories support to ld

2018-05-08 Thread wilson at gcc dot gnu.org
|--- |FIXED Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org --- Comment #17 from Jim Wilson --- Patch on mainline. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug

[Bug gas/23219] [RISCV] Internal error with .align and .option norelax

2018-05-23 Thread wilson at gcc dot gnu.org
||2018-05-24 CC||wilson at gcc dot gnu.org Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- I see several problems

[Bug gas/23219] [RISCV] Internal error with .align and .option norelax

2018-05-24 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23219 Jim Wilson changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug ld/23244] RISC-V 64 relocation truncated to fit in case of undefined weak references

2018-05-29 Thread wilson at gcc dot gnu.org
||2018-05-30 CC||wilson at gcc dot gnu.org Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- I see the problem. This is

[Bug ld/22756] Linker relaxation miscalculates symbol addresses on riscv

2018-06-01 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22756 --- Comment #8 from Jim Wilson --- Linker relaxation that deletes code is O(m*n) where m is the number of relocations and n is the number of symbols. There have been complaints about this. This makes the RISC-V linker slower than other targe

[Bug ld/23244] RISC-V 64 relocation truncated to fit in case of undefined weak references

2018-06-03 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23244 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug gas/23305] RISC-V illegal operands with lla and .set

2018-06-18 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23305 --- Comment #2 from Jim Wilson --- lla is only valid for symbol addresses. It isn't meant to be used for constants. But that is an interesting testcase. Did this come from real code? If so then we need to fix this. You can make medlow fai

[Bug gas/23305] RISC-V illegal operands with lla and .set

2018-06-19 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23305 Jim Wilson changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug gas/23451] RISC-V gas aborts with "Error: unknown default architecture `'" in GCC configure tests

2018-07-27 Thread wilson at gcc dot gnu.org
||2018-07-27 Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #3 from Jim Wilson --- I did a build test, but I see now that it builds but doesn't run. Annoying, but this is easy to fi

[Bug gas/23451] RISC-V gas aborts with "Error: unknown default architecture `'" in GCC configure tests

2018-07-27 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23451 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/23825] Linker creates COPY relocs for reference to TLS symbols

2018-10-25 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23825 --- Comment #1 from Jim Wilson --- This is a feature of the RISC-V toolchain, which apparently isn't supported by any other toolchain, and which is known to be broken, but we don't yet know if it is a gcc, binutils, ld.so, or something else bu

[Bug ld/23825] Linker creates COPY relocs for reference to TLS symbols

2018-10-25 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23825 Jim Wilson changed: What|Removed |Added Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org

[Bug gas/23956] RISC-V 4-operand add doesn't check for %tprel_add

2018-12-06 Thread wilson at gcc dot gnu.org
||2018-12-07 Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- I consider it a bug, but not serious enough that I had gotten around to trying to fix it yet. The

[Bug gas/23956] RISC-V 4-operand add doesn't check for %tprel_add

2018-12-07 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23956 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug gas/23954] Use of unknown relocation function causes segfault

2018-12-07 Thread wilson at gcc dot gnu.org
||2018-12-08 Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- The problem is the extra register, not the unknown relocation function. I get the same error with

[Bug gas/23954] Use of unknown relocation function causes segfault

2018-12-10 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23954 Jim Wilson changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2019-02-18 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2019-02-18 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 --- Comment #2 from Jim Wilson --- Another possibility here is a broken linker script that isn't respecting section alignment. -- You are receiving this mail because: You are on the CC list for the bug. __

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

2019-02-19 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24226 --- Comment #4 from Jim Wilson --- Yes, I'd call this a compiler bug. It is triggered when we have a long long inside a packed structure compiled for a 32-bit target, where the long long must be partially contained in the first word of the st

[Bug binutils/24365] Crash due to RISC-V relocation

2019-03-20 Thread wilson at gcc dot gnu.org
||2019-03-20 Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- I never tried this with a global symbol. This only works for local symbols. sym is only set for local

[Bug binutils/24365] Crash due to RISC-V relocation

2019-03-21 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24365 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/24389] can't link soft-float modules with double-float modules

2019-03-27 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24389 --- Comment #1 from Jim Wilson --- David Abdurachmanov reported the same problem with Fedora over the weekend, but I wasn't able to look at it at the time as SiFive building power was off for maintenance. Building glib to reproduce, I see tha

[Bug ld/24389] can't link soft-float modules with double-float modules

2019-03-28 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24389 --- Comment #4 from Jim Wilson --- I don't see a way to specify this in the linker either. I looked at gas, and noticed that it is broken also, but slightly differently. Gas is defaulting to rv64g/lp64d when configured for 64-bit, and rv32g/

[Bug ld/24389] can't link soft-float modules with double-float modules

2019-04-01 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24389 Jim Wilson changed: What|Removed |Added Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org

[Bug ld/24389] can't link soft-float modules with double-float modules

2019-04-02 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24389 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/24426] Binutils 2.28.1 segfault when presented (any) linker script on riscv64

2019-04-08 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24426 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug ld/24426] Binutils 2.28.1 segfault when presented (any) linker script on riscv64

2019-04-09 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24426 --- Comment #3 from Jim Wilson --- I tried to reproduce with no luck. I think that there are too many things broken on your end. I had to hack up crt0.S to remove the required support for __global_pointer$, and I had to hack your linker scri

[Bug ld/24426] Binutils 2.28.1 segfault when presented (any) linker script on riscv64

2019-04-09 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24426 --- Comment #7 from Jim Wilson --- An empty linker script isn't expected to work. This will probably fail for every linker target. It fails for x86_64-linux for instance. rohan:2037$ uname -a Linux rohan 4.15.0-47-generic #50-Ubuntu SMP Wed

[Bug ld/24426] Binutils 2.28.1 segfault when presented (any) linker script on riscv64

2019-04-09 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24426 --- Comment #9 from Jim Wilson --- RISC-V is an ISA. The amount of memory that can be accessed depends on the ISA implementation that you are using. This varies from one implementation to another. But most 64-bit processors do not have 64 a

[Bug ld/24673] [RISCV] -fPIC -pie and -fPIC -no-pie create unexpected R_RISCV_NONE R_RISCV_DTPMOD64 relocations

2019-06-12 Thread wilson at gcc dot gnu.org
||2019-06-12 CC||wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- The DTPMOD64 reloc is required for a shared library, and a PIE program is basically a shared library with a few

[Bug ld/24673] [RISCV] -fPIC -pie and -fPIC -no-pie create unexpected R_RISCV_NONE R_RISCV_DTPMOD64 relocations

2019-06-12 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24673 --- Comment #2 from Jim Wilson --- The issue with the R_RISCV_NONE appears to be that we are pre-allocating space for dynamic relocs, and accidentally allocating one more than we need. This space is apparently cleared someplace. So it ends u

[Bug ld/24673] [RISCV] -fPIC -pie and -fPIC -no-pie create unexpected R_RISCV_NONE R_RISCV_DTPMOD64 relocations

2019-06-13 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24673 --- Comment #3 from Jim Wilson --- Via IRC, elfnn-riscv.c circa line 563 has case R_RISCV_TLS_GOT_HI20: if (bfd_link_pic (info)) info->flags |= DF_STATIC_TLS; where this should be bfd_link_dll instead of bfd_link_

[Bug ld/24676] [RISCV] Redundant R_RISCV_DTPMOD* R_RISCV_DTPREL* resulted from Glocal Dynamic -> Local Exec relaxation

2019-06-13 Thread wilson at gcc dot gnu.org
||2019-06-13 CC||wilson at gcc dot gnu.org Depends on||24673 Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- Assuming that the MIPS port is handling this right, then

[Bug ld/24673] [RISCV] -fPIC -pie and -fPIC -no-pie create unexpected R_RISCV_NONE R_RISCV_DTPMOD64 relocations

2019-06-13 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24673 Jim Wilson changed: What|Removed |Added Blocks||24676 Referenced Bugs: https://sourcew

[Bug ld/24678] New: RISC-V pcrel relocs and abs global pointer variable

2019-06-13 Thread wilson at gcc dot gnu.org
Component: ld Assignee: unassigned at sourceware dot org Reporter: wilson at gcc dot gnu.org Target Milestone: --- Reported via IRC. Compiling a trivial program as PIE, I get hifiveu017:1201$ gcc -pie -fpic tmp.c hifiveu017:1202$ readelf -s a.out | grep global_pointer 65

[Bug ld/24678] RISC-V pcrel relocs and abs global pointer variable

2019-06-13 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24678 Jim Wilson changed: What|Removed |Added Target||riscv*-*-* -- You are receiving this ma

[Bug ld/24678] RISC-V pcrel relocs and abs global pointer variable

2019-06-13 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24678 --- Comment #1 from Jim Wilson --- The section for linker script defined variables is set in set_sym_sections, via update_definedness, which uses section_for_dot. Since we are computing the __global_pointer$ value near the end of the linker s

[Bug ld/24683] New: RISC-V call and callplt reloc handling

2019-06-14 Thread wilson at gcc dot gnu.org
Assignee: unassigned at sourceware dot org Reporter: wilson at gcc dot gnu.org Target Milestone: --- Another one from the lld folks. Given .global test, foo, bar, baz test: call foo call bar call bar@plt call baz@plt and compiling it with gcc -o call-plt

[Bug ld/24685] [RISCV] R_RISCV_CALL_PLT should not create a canonical PLT in -no-pie mode

2019-06-24 Thread wilson at gcc dot gnu.org
||2019-06-25 CC||wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- Looks like the problem is in riscv_elf_finish_dynamic_symbol where we have /* If the symbol is weak, we

[Bug binutils/24739] RISC-V Disassembler should default to little endian

2019-06-26 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24739 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug binutils/24739] RISC-V Disassembler should default to little endian

2019-06-26 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24739 Jim Wilson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug binutils/22941] binutils build fails if intl/plural.y is newer than intl/plural.c

2019-07-07 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=22941 Jim Wilson changed: What|Removed |Added CC||pjb at informatimago dot com --- Comment

[Bug binutils/24029] Failure to compile plural.c (libintl) on Mojave.

2019-07-07 Thread wilson at gcc dot gnu.org
||wilson at gcc dot gnu.org Resolution|--- |DUPLICATE --- Comment #1 from Jim Wilson --- Duplicate of 22941. intl does't build with bison-3.0.4. *** This bug has been marked as a duplicate of bug 22941 *** -- You are receiving this mail be

[Bug ld/23825] Linker creates COPY relocs for reference to TLS symbols

2019-08-31 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23825 --- Comment #3 from Jim Wilson --- I got an internal bug report with a simplified testcase related to this, took another look, and found the problem. hifiveu017:1097$ cat tmp.c #include extern __thread int a; int main (void) {printf ("a = %d

[Bug ld/23825] Linker creates COPY relocs for reference to TLS symbols

2019-09-03 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23825 Jim Wilson changed: What|Removed |Added Status|NEW |ASSIGNED --- Comment #5 from Jim Wilson

[Bug ld/24983] RISC-V GP linker relaxation is not performed with -nostdlib

2019-09-10 Thread wilson at gcc dot gnu.org
||2019-09-10 CC||wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jim Wilson --- Commentary copied from the gcc bug report... This is an edge condition and an accident of circumstances. When

[Bug ld/24992] RISC-V: partial relaxing against global pointer with sdata section alignment

2019-09-11 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24992 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug binutils/24993] RISC-V: Address 0x00000000000xxxxx is out of bounds when "objdump -D"

2019-09-11 Thread wilson at gcc dot gnu.org
||wilson at gcc dot gnu.org Resolution|--- |INVALID --- Comment #1 from Jim Wilson --- the problem is that you are using objdump -D, and this is almost always the wrong thing to do. The correct option is "-d". -D will dump data sections

[Bug ld/24983] RISC-V GP linker relaxation is not performed with -nostdlib

2019-09-11 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24983 Jim Wilson changed: What|Removed |Added CC||yitingwang16 at outlook dot com --- Comm

[Bug ld/24992] RISC-V: partial relaxing against global pointer with sdata section alignment

2019-09-11 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24992 Jim Wilson changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug ld/24992] RISC-V: partial relaxing against global pointer with sdata section alignment

2019-09-12 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24992 --- Comment #4 from Jim Wilson --- It is the same underlying problem. Addresses can increase by up to section alignment after relaxation, so we have to reduce gp range by the alignment of the largest section in between gp and the variable, bu

[Bug ld/24983] RISC-V GP linker relaxation is not performed with -nostdlib

2019-09-12 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24983 --- Comment #3 from Jim Wilson --- There is another related problem reported here https://github.com/riscv/riscv-gnu-toolchain/issues/497 -- You are receiving this mail because: You are on the CC list for the bug. ___

[Bug binutils/24993] RISC-V: Address 0x00000000000xxxxx is out of bounds when "objdump -D"

2019-09-12 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24993 Jim Wilson changed: What|Removed |Added Status|RESOLVED|REOPENED Last reconfirmed|

[Bug ld/24992] RISC-V: partial relaxing against global pointer with sdata section alignment

2019-09-17 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24992 --- Comment #6 from Jim Wilson --- See comment #4 that says "Unless gp and the variable are in the same section, in which case we can ignore the problem." -- You are receiving this mail because: You are on the CC list for the bug. __

[Bug binutils/25181] RISC-V: Linker relaxation may fail if there are R_RISCV_ALIGN type relocations

2019-11-11 Thread wilson at gcc dot gnu.org
||2019-11-12 CC||wilson at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #4 from Jim Wilson --- The way that this should work is that if the call crosses section boundaries, then we need to use the max

[Bug binutils/25181] RISC-V: Linker relaxation may fail if there are R_RISCV_ALIGN type relocations

2019-11-11 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25181 --- Comment #5 from Jim Wilson --- Created attachment 12071 --> https://sourceware.org/bugzilla/attachment.cgi?id=12071&action=edit untested patch to fix _bfd_riscv_relax_call -- You are receiving this mail because: You are on the CC list

[Bug binutils/25181] RISC-V: Linker relaxation may fail if there are R_RISCV_ALIGN type relocations

2019-11-11 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25181 --- Comment #6 from Jim Wilson --- You can create a patch with git diff and then attach it to the bug report. It needs to be mailed to the binutils list if it gets checked in, but you can always ask someone else to do that for you. Contribut

[Bug binutils/25181] RISC-V: Linker relaxation may fail if there are R_RISCV_ALIGN type relocations

2019-11-12 Thread wilson at gcc dot gnu.org
|--- |FIXED Assignee|unassigned at sourceware dot org |wilson at gcc dot gnu.org --- Comment #9 from Jim Wilson --- Fixed on mainline. -- You are receiving this mail because: You are on the CC list for the bug.

[Bug ld/23825] Linker creates COPY relocs for reference to TLS symbols

2019-11-19 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=23825 --- Comment #9 from Jim Wilson --- This is being discussed in https://github.com/riscv/riscv-elf-psabi-doc/issues/122 which is the proper place to discuss RISC-V ABI issues. -- You are receiving this mail because: You are on the CC list f

[Bug gas/25264] RISC-V option norvc: linker complains "14 bytes required for alignment to 16-byte boundary, but only 12 present"

2019-12-10 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25264 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug ld/25258] RISC-V: relocation truncated to fit: R_RISCV_GPREL_I against `.LANCHOR2'

2019-12-10 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25258 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment

[Bug ld/25205] relocation truncated to fit: R_RISCV_JAL against undefined symbol `pthread_once'

2019-12-10 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25205 --- Comment #2 from Jim Wilson --- I made an attempt to reproduce this, but I don't build llvm very often (cough) so I don't really know what I'm doing. I can build llvm in a one stage build on a riscv fedora system. When I tried a two stage

[Bug ld/25205] relocation truncated to fit: R_RISCV_JAL against undefined symbol `pthread_once'

2019-12-18 Thread wilson at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25205 --- Comment #7 from Jim Wilson --- I can reproduce with your object files. I had to add a -B option to find crtbegin.o and libgcc.a. Maybe something wrong with clang on my system. Anyways, what I see is that in _bfd_riscv_relax_section, if

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