Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: avieira at gcc dot gnu.org
Target Milestone: ---
Hello,
When trying to assemble a load pseudo-operation for Cortex-M23 gas currently
incorrectly errors out:
$ cat t.s
ldr r0, =(0x30
https://sourceware.org/bugzilla/show_bug.cgi?id=24559
Andre Vieira changed:
What|Removed |Added
Target||arm-*
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https://sourceware.org/bugzilla/show_bug.cgi?id=24559
Andre Vieira changed:
What|Removed |Added
Assignee|unassigned at sourceware dot org |avieira at gcc dot
gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=24559
Andre Vieira changed:
What|Removed |Added
Build||2.27, 2.28, 2.29, 2.30,
https://sourceware.org/bugzilla/show_bug.cgi?id=24559
--- Comment #1 from Andre Vieira ---
Patch up for review on the mailing list
https://sourceware.org/ml/binutils/2019-05/msg00201.html
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||avieira at gcc dot gnu.org
Resolution|--- |FIXED
--- Comment #2 from Andre Vieira ---
I messed up the commit message for bfd/ChangeLog in
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h
https://sourceware.org/bugzilla/show_bug.cgi?id=24559
--- Comment #3 from Andre Vieira ---
Backported this to 2.32, not planning any other backports. OK To close ticket?
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b
ty: normal
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: avieira at gcc dot gnu.org
Target Milestone: ---
GAS -mfpu command-line option and .fpu assembler directive reset the MVE
feature bits but can't set it. I.e. -mf
|unassigned at sourceware dot org |avieira at gcc dot
gnu.org
Build||2.33
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MVE architecturally demands the implementation of the DSP extensions, so +mve
should also enable DSP instructions like uadd8 r0, r1, r2.
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https://sourceware.org/bugzilla/show_bug.cgi?id=25472
Andre Vieira changed:
What|Removed |Added
Assignee|unassigned at sourceware dot org |avieira at gcc dot
gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25472
Andre Vieira changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: avieira at gcc dot gnu.org
Target Milestone: ---
The following assembly will be wrongly rejected if mve is enabled:
.syntax unified
.text
itt lt
vsublt.f32 s0, s1, s2
vaddlt.f32 s0, s1, s2
https://sourceware.org/bugzilla/show_bug.cgi?id=25660
Andre Vieira changed:
What|Removed |Added
Assignee|unassigned at sourceware dot org |avieira at gcc dot
gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25376
Andre Vieira changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
https://sourceware.org/bugzilla/show_bug.cgi?id=25660
Andre Vieira changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: avieira at gcc dot gnu.org
Target Milestone: ---
When parsing the following with -march=armv8.1-m.main+mve.fp, GAS currently
wrongfully rejects it.
.syntax unified
.text
it lt
vmullt.f32 s0, s1, s2
In my original
https://sourceware.org/bugzilla/show_bug.cgi?id=25863
Andre Vieira changed:
What|Removed |Added
Assignee|unassigned at sourceware dot org |avieira at gcc dot
gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25863
Andre Vieira changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://sourceware.org/bugzilla/show_bug.cgi?id=25992
Andre Vieira changed:
What|Removed |Added
CC||avieira at gcc dot gnu.org
https://sourceware.org/bugzilla/show_bug.cgi?id=25992
--- Comment #11 from Andre Vieira ---
Nick were you able to reproduce this locally? I have tried a bunch of different
arm targets and branches but could not reproduce this behaviour, which is
weird... Might be there is some other issue masking
https://sourceware.org/bugzilla/show_bug.cgi?id=25992
--- Comment #14 from Andre Vieira ---
Oh doh... I was looking at the Tag_CPU_arch instead of arch_profile. Sorry
Alexander.
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https://sourceware.org/bugzilla/show_bug.cgi?id=26858
Andre Vieira changed:
What|Removed |Added
CC||avieira at gcc dot gnu.org
Last
https://sourceware.org/bugzilla/show_bug.cgi?id=26858
--- Comment #4 from Andre Vieira ---
I'll wait a week or so before backporting to affected branches.
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https://sourceware.org/bugzilla/show_bug.cgi?id=26858
Andre Vieira changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
y: P2
Component: binutils
Assignee: unassigned at sourceware dot org
Reporter: avieira at gcc dot gnu.org
Target Milestone: ---
Hi,
Similar to https://github.com/llvm/llvm-project/issues/56738 when we use
Binutil's strip to strip a binary optimized with BOLT i
https://sourceware.org/bugzilla/show_bug.cgi?id=32324
Andre Vieira changed:
What|Removed |Added
Target||aarch64-none-linux-gnu
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https://sourceware.org/bugzilla/show_bug.cgi?id=32324
--- Comment #1 from Andre Vieira ---
I did a bit more investigation and looking through the sections in the warning
I noticed something odd.
readelf --sections shows me:
Section Headers:
[Nr] Name Type Address
https://sourceware.org/bugzilla/show_bug.cgi?id=32324
--- Comment #2 from Andre Vieira ---
Further investigations showed that things started to go wrong when the LOAD
header in question is given an offset of where the previous header left off,
which is normally fine, but this is severely under th
https://sourceware.org/bugzilla/show_bug.cgi?id=32324
Andre Vieira changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
https://sourceware.org/bugzilla/show_bug.cgi?id=32324
--- Comment #6 from Andre Vieira ---
Scrap that, probably best not to backport.
Oh and thank you Alan!
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