[Bug binutils/25213] [RISCV] SUB6 applied without 6-bit mask

https://sourceware.org/bugzilla/show_bug.cgi?id=25213 --- Comment #1 from Luís Marques --- Oops, apparently I mistyped some numbers in my previous description. Corrected: - Expected value: keep the upper 2 bits and write the computed relocation value to the lower 6 bits: 0x7E - (0x42 & 0xC0) |

[Bug gas/25212] [RISCV] gas doesn't flag invalid march and mabi combinations

https://sourceware.org/bugzilla/show_bug.cgi?id=25212 Luís Marques changed: What|Removed |Added CC||luismarques at lowrisc dot org

[Bug binutils/25213] [RISCV] SUB6 applied without 6-bit mask

https://sourceware.org/bugzilla/show_bug.cgi?id=25213 Luís Marques changed: What|Removed |Added CC||luismarques at lowrisc dot org

[Bug binutils/25213] New: [RISCV] SUB6 applied without 6-bit mask

Component: binutils Assignee: unassigned at sourceware dot org Reporter: luismarques at lowrisc dot org Target Milestone: --- Created attachment 12087 --> https://sourceware.org/bugzilla/attachment.cgi?id=12087&action=edit object file with DWARF data with field with R_RIS

[Bug gas/25212] [RISCV] gas doesn't flag invalid march and mabi combinations

https://sourceware.org/bugzilla/show_bug.cgi?id=25212 Luís Marques changed: What|Removed |Added CC||wilson at gcc dot gnu.org -- You are

[Bug gas/25212] New: [RISCV] gas doesn't flag invalid march and mabi combinations

erity: minor Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: luismarques at lowrisc dot org Target Milestone: --- This, by itself, isn't ideal: $ touch test.s $ riscv32-unknown-elf-as -march=rv32i -mabi=ilp32d test.

[Bug binutils/24365] Crash due to RISC-V relocation

https://sourceware.org/bugzilla/show_bug.cgi?id=24365 Luís Marques changed: What|Removed |Added CC||luismarques at lowrisc dot org

[Bug binutils/24365] New: Crash due to RISC-V relocation

Assignee: unassigned at sourceware dot org Reporter: luismarques at lowrisc dot org Target Milestone: --- (Using the RISC-V GNU toolchain built from the commit afcc8bc655d30cf6af054ac1d3f5f89d0627aa79 of https://github.com/riscv/riscv-gnu-toolchain.git, commit

[Bug gas/23954] Use of unknown relocation function causes segfault

https://sourceware.org/bugzilla/show_bug.cgi?id=23954 Luís Marques changed: What|Removed |Added CC||wilson at gcc dot gnu.org -- You are

[Bug gas/23956] RISC-V 4-operand add doesn't check for %tprel_add

https://sourceware.org/bugzilla/show_bug.cgi?id=23956 Luís Marques changed: What|Removed |Added CC||wilson at gcc dot gnu.org -- You are

[Bug gas/23956] New: RISC-V 4-operand add doesn't check for %tprel_add

y: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: luismarques at lowrisc dot org Target Milestone: --- In RISC-V assembly, there's a fictitious 4-operand ADD that's used to add a TP-relative relocation. It's usually used like "add a0,a0

[Bug gas/23954] New: Use of unknown relocation function causes segfault

Component: gas Assignee: unassigned at sourceware dot org Reporter: luismarques at lowrisc dot org Target Milestone: --- Tested with gas built from riscv-gnu-toolchain (commit 411d1345507e5313c3575720f128be9e6c0ed941, riscv-binutils commit