[Bug ld/30437] aarch64: RELA relocations don't ignore section content as they should

https://sourceware.org/bugzilla/show_bug.cgi?id=30437 Michael Matz changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug ld/30437] aarch64: RELA relocations don't ignore section content as they should

https://sourceware.org/bugzilla/show_bug.cgi?id=30437 --- Comment #3 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Michael Matz : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=13a3cad698b3a757b1fcc938cc33e09a364ea47a commit 13a3cad698b3a757b1fcc938cc3

[Bug ld/25694] R_RISCV_TPREL_HI20 relocations cause riscv64 to add TEXTREL bit on executables

https://sourceware.org/bugzilla/show_bug.cgi?id=25694 --- Comment #5 from Andreas Schwab --- This still generates a spurious R_RISCV_NONE relocation for the pr22263-1 test. -- You are receiving this mail because: You are on the CC list for the bug.

[Bug ld/22263] -fpie -pie generates dynamic relocations in text section

https://sourceware.org/bugzilla/show_bug.cgi?id=22263 Andreas Schwab changed: What|Removed |Added See Also||https://sourceware.org/bugz

[Bug ld/25694] R_RISCV_TPREL_HI20 relocations cause riscv64 to add TEXTREL bit on executables

https://sourceware.org/bugzilla/show_bug.cgi?id=25694 Andreas Schwab changed: What|Removed |Added See Also||https://sourceware.org/bugz

[Bug ld/22263] -fpie -pie generates dynamic relocations in text section

https://sourceware.org/bugzilla/show_bug.cgi?id=22263 Andreas Schwab changed: What|Removed |Added Target|tilegx,tilepro,sparc,alpha |tilegx,tilepro,sparc,alpha,