Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-08-26 Thread Mark Kettenis
> Date: Wed, 26 Aug 2020 21:54:30 + > From: a...@sdf.org > > > > reg |= H3_CPUX_CLK_SRC_SEL_OSC24M; > > > SXIWRITE4(sc, H3_CPUX_AXI_CFG_REG, reg); > > > + /* Must wait at least 8 cycles of the current clock. */ > > > + delay(1); > > > > > > error

Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-08-26 Thread adr
> > reg |= H3_CPUX_CLK_SRC_SEL_OSC24M; > > SXIWRITE4(sc, H3_CPUX_AXI_CFG_REG, reg); > > + /* Must wait at least 8 cycles of the current clock. */ > > + delay(1); > > > > error = sxiccmu_h3_set_frequency(sc, H3_CLK_PLL_CPUX, freq); > > > >