[PATCH 01/25] drm/amd/display: 3.2.12

From: Steven Chiu Signed-off-by: Steven Chiu Reviewed-by: Yongqiang Sun Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ee70540..f80f52

[PATCH 06/25] drm/amd/display: refactor reg_update

From: Tony Cheng [why] separate register access from logic to allow us abstract register sequences [how] consolidate mask and value first then apply to register. Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 36 ++

[PATCH 09/25] drm/amd/display: Fix for NULL ramp pointer crashing driver

From: Joshua Aberback [Why] In certain scenarios the ramp parameter come in as NULL, which crashes because this function doesn't guard properly in the early return. [How] - parameter mapUserRamp should be the guard (false means no ramp) - remove checking ramp in early return Signed-off-by: Josh

[PATCH 08/25] drm/amd/display: Redefine DMCU_SCRATCH to identify DMCU state

From: Martin Tsai [why] To resume system before entering S0i3 completely will cause PSP not reload DMCU FW since there is not HW power state change. In this case, driver cannot get correct DMCU version from IRAM since driver override it and DMCU didn't reload to update it. It makes driver return

[PATCH 04/25] drm/amd/display: fix CTS 4.2.2.8

From: abdoulaye berthe [Why] 1-Test equipment does not reset test automation flag after completing current test causing the next test to fail. 2.When test request is empty, we shouldn't ack the test. [How] 1-Driver should always clear test equipment automation test request when request is comple

[PATCH 21/25] drm/amd/display: Rename configure_encoder to enc1_configure_encoder

From: Dmytro Laktyushkin Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) d

[PATCH 05/25] Revert "drm/amd/display: Signal hw_done() after waiting for flip_done()"

From: Leo Li This reverts commit 717276b9256f5d97b43e53adca1670cee2c45db2. The reverted patch was a workaround that addressed an issue fixed by: 4364bcb2cd21 ("drm: Get ref on CRTC commit object when waiting for flip_done") Signed-off-by: Leo Li Reviewed-by: Nicholas Kazlauskas --- drivers/g

[PATCH 07/25] drm/amd/display: fix PME notification not working in RV desktop

From: Charlene Liu [Why] PPLIB not receive the PME when unplug. Signed-off-by: Charlene Liu Reviewed-by: Chris Park Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/d

[PATCH 17/25] drm/amd/display: dal-pplib interface refactor dal part

From: hersen wu [WHY] clarify dal input parameters to pplib interface, remove un-used parameters. dal knows exactly which parameters needed and their effects at pplib and smu sides. current dal sequence for dcn1_update_clock to pplib: 1.smu10_display_clock_voltage_request for dcefclk 2.smu10_di

[PATCH 11/25] drm/amd/display: Fix disabled cursor on top screen edge

From: Nicholas Kazlauskas [Why] The cursor vanishes when touching the top of edge of the screen for Raven on Linux. This occurs because the cursor height is not taken into account when deciding to disable the cursor. [How] Factor in the cursor height into the cursor calculations - and mimic the

[PATCH 10/25] drm/amd/display: Set link rate set if eDP ver >= 1.4.

From: Derek Lai [Why] If eDP ver >= 1.4, the Source device must use LINK_RATE_SET. [How] Get LINK_RATE_SET by reading DPCD 10h-1fh, then write DPCD 00115h before link training. Signed-off-by: Derek Lai Reviewed-by: Tony Cheng Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/core/dc_link_

[PATCH 18/25] drm/amd/display: fix warning on raven hotplug

From: Roman Li [Why] Hotplug on raven results in REG_WAIT_TIMEOUT warning due to failing attempt to lock disabled otg for the hubp interdependent pipes programming. [How] Don't setup pipe interdependencies for disabled otg. Also removed the unnecessary duplicate logic checks. Signed-off-by: Rom

[PATCH 22/25] drm/amd/display: Add new infopacket definition

From: Bayan Zabihiyan Modify freesync module to build VTEM infopackets when in HdmiVRR mode Signed-off-by: Bayan Zabihiyan Reviewed-by: Jun Lei Acked-by: Leo Li --- .../drm/amd/display/modules/freesync/freesync.c| 94 -- .../gpu/drm/amd/display/modules/inc/mod_freesyn

[PATCH 02/25] drm/amd/display: Fix missing hwss function for dce

From: Joshua Aberback [Why] The driver will crash on dce hardware due to a null function pointer. [How] - bring back "program_csc_matrix" functionality as "program_output_csc" for dce110 - dce110 doesn't use the "opp_id" parameter, so use 0 when there's no hubp Signed-off-by: Joshua Aberback R

[PATCH 15/25] drm/amd/display: Change from aux_engine to dce_aux

From: David Francis [Why] The aux_engine struct is needlessly complex and is defined multiple times. It contains function pointers that each have only one version and are called only from inside dce_aux. [How] Replace aux_engine with a new struct called dce_aux. Remove all function pointers and

[PATCH 19/25] drm/amd/display: dp interlace MSA timing programming for Interlace mode.

From: Charlene Liu [Why] DP compliance box shows wrong MSA data. Signed-off-by: Charlene Liu Reviewed-by: Jun Lei Acked-by: Leo Li --- .../drm/amd/display/dc/dce/dce_stream_encoder.c| 65 - .../amd/display/dc/dcn10/dcn10_stream_encoder.c| 68 +-

[PATCH 24/25] drm/amd/display: Check for NULL when creating gamma struct

From: Krunoslav Kovac [Wjy&How] Some stress test is causing unexpected memory allocation failure. This prevents null dereference but there will likely be problems later, hard to gracefully handle memalloc fail for critical objects. Signed-off-by: Krunoslav Kovac Reviewed-by: Anthony Koo Acked-

[PATCH 03/25] drm/amd/display: Pack DMCU iRAM alignment

From: Josip Pavic [Why] When the DMCU's iRAM definition was moved to the newly created power_helpers, a #pragma pack was lost, causing the iRAM to be misaligned [How] Restore the #pragma pack Signed-off-by: Josip Pavic Reviewed-by: Anthony Koo Acked-by: Leo Li --- drivers/gpu/drm/amd/displa

[PATCH 20/25] drm/amd/display: add workaround for 4k video underflow

From: Eric Yang [Why] On DCN1, there is an issue where on high BW config on single channel systems, underflow will be observed if DCC is disabled. This issue can be observed on several use cases. For this particular case, it is observed when playing 4k video on 4k desktop with video downscaled to

[PATCH 13/25] drm/amd/display: Shift dc link aux to aux_payload

From: David Francis [Why] aux_payload should be the struct used inside dc to start aux transactions. This will allow the old aux interface to be seamlessly replaced. [How] Add three fields to aux_payload: reply, mot, defer_delay This will mean that aux_payload has all data required to submit a

[PATCH 12/25] drm/amd/display: 3.2.13

From: Steven Chiu Signed-off-by: Steven Chiu Reviewed-by: Yongqiang Sun Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1c46249..98f716

[PATCH 00/25] DC Patches Jan 08, 2019

From: Leo Li Summary of change: * AUX interface cleanup and refactor * Fix potential warning storm on Raven * Fix vanishing cursor bug on Raven Bayan Zabihiyan (1): drm/amd/display: Add new infopacket definition Charlene Liu (2): drm/amd/display: fix PME notification not working in RV desk

[PATCH 14/25] drm/amd/display: Switch ddc to new aux interface

From: David Francis [Why] The old aux interface goes through i2caux and the aux_engine and engine function pointers. The multiple layers of indirection make it hard to tell waht is happening. The aux algorithm does not need to be this complicated: attempt to submit the request. If you get an a

[PATCH 23/25] drm/amd/display: Check if registers are available before accessing

From: Eric Bernstein Check if VERT_FILTER_INIT_BOT and BLACK_OFFSET registers exists in the DCN SCL IP block before trying to access. Signed-off-by: Eric Bernstein Reviewed-by: Dmytro Laktyushkin Acked-by: Leo Li --- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 42 ---

[PATCH 25/25] drm/amd/display: 3.2.14

From: Steven Chiu Signed-off-by: Steven Chiu Reviewed-by: Yongqiang Sun Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 98f716be..f362b

[PATCH] drm/amd/display: Fully remove i2caux folder

From: Leo Li This is a follow up to: e28e1490794d ("drm/amd/display: Remove i2caux folder") Some files were still left, so delete all of them. CC: David Francis CC: Harry Wentland Signed-off-by: Leo Li --- drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 99 .../dc/i2caux/dce110/i

[PATCH] drm/amd/display: eDP fast bootup does not work for pre-raven asic

From: hersen wu [Why] bios will light up eDP before sw driver loaded. sw driver will check if eDP lighted up by bios by reading BIOS_SCRATCH_3. If yes, sw driver will not power down eDP power, phy to save time. definition of BIOS_SCRATCH_3 are missed for pre-raven asic. this cuase eDP fast boot u

[PATCH 03/20] drm/amd/display: Simplify underscan and ABM commit

From: David Francis [Why] Underscan and ABM are connector properties but require updates to DC stream state. Previously, on updates to these properties the affected stream and all its planes were committed. This is unnecessary; only a few fields on the stream need to be changed. [How] If scalin

[PATCH 02/20] drm/amd/display: Introduce DC VM interface

From: Eryk Brol Virtual memory allows display to support flipping to surfaces which are not allocated contiguously in memory with physical addresses, instead a 1-4 level page table is used. This is beneficial because it allows the scattering of large surfaces to improve memory efficiency and sec

[PATCH 00/20] DC Patches Jan 22, 2019

From: Leo Li Summary of change: * Fixes for pageflipping logic * Multiplane flipping support * Make it more atomic * Fix CRC capture on pipes with no active vblank reference * Simplify commit for scaling and ABM changes David Francis (5): drm/amd/display: Simplify underscan and ABM co

[PATCH 01/20] drm/amd/display: Restructure DCN10 hubbub

From: Eryk Brol [Why] Change DCN10 hubbub to use hubbub as a base and allow all future DCN hubbubs to do the same instead of using DCN10_hubbub. This increases readability and doesn't require future hubbubs to inherit anything other than the base hubbub struct. [How] Create separate DCN10_hubbub

[PATCH 06/20] drm/amd/display: Let updates with no scaling changes be fast

From: David Francis [Why] DC was assuming that any surface_update->scaling_info meant the update was at least medium. However, if nothing has changed there is no scaling to program, so there is no problem with the update being fast [How] If every update flag is not set, the update is fast Sign

[PATCH 11/20] drm/amd/display: Default to linear output gamma

From: Krunoslav Kovac [Why] Our output TF calculation doesn't work if no user-specified gamma correction. Normally, user provides this, but driver sohuld just assume default (linear) gamma otherwise. [How] Remove output TF dependency on user gamma being provided. Signed-off-by: Krunoslav Kovac

[PATCH 08/20] drm/amd/display: Update DMCU versioning mechanism

From: Josip Pavic [Why] Current date based versioning doesn't tell us about feature version and build version, and is not useful for debug. [How] Add versioning based on feature and build Signed-off-by: Josip Pavic Reviewed-by: Anthony Koo Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc

[PATCH 04/20] drm/amd/display: Know what a pageflip is

From: David Francis [Why] We were assuming that any commit with allow_modeset == false was a pageflip. This was against drm intention and only worked by sheer luck [How] A pageflip is the change from one framebuffer to another Signed-off-by: David Francis Reviewed-by: Harry Wentland Reviewed

[PATCH 09/20] drm/amd/display: Create switching mechanism for ABM 2.2

From: Josip Pavic [Why] Need method of detecting which version of the DMCU FW is loaded and load the appropriate iRAM. [How] Create definition for ABM 2.2 iRAM, and load it if the DMCU FW version number matches the ABM 2.2 version; otherwise load ABM 2.1 iRAM. Signed-off-by: Josip Pavic Review

[PATCH 07/20] drm/amd/display: Perform plane updates only when needed

From: David Francis [Why] Our old logic: if pageflip, update freesync and plane address. Otherwise, update everything. This over-updated on non-pageflip cases, and it failed to update if pageflip and non-pageflip changes occurred on the same commit [How] Update flip_addrs on pageflips. Update sc

[PATCH 10/20] drm/amd/display: Fix use of uninitialized union

From: John Barberiz [Why] An uninitialized variable would randomly initialize to a large value. This caused enough delay to fail DP Compliance Test 400.2.1. [How] Initialize the variable. Signed-off-by: John Barberiz Reviewed-by: Wenjing Liu Acked-by: Leo Li --- drivers/gpu/drm/amd/display/

[PATCH 05/20] drm/amd/display: Call into DC once per multiplane flip

From: David Francis [Why] amdgpu_dm_commit_planes was performing multi-plane flips incorrectly: It waited for vblank once per flipped plane It prepared flip ISR and acquired the corresponding vblank ref once per plane, although it closed ISR and put the ref once per crtc It called into dc once

[PATCH 14/20] drm/amd/display: take dpms_off into account for edp turn off logic

From: Eric Yang [why] Previously we incorrectly skipped backlight control when stream is present but dpms_off = true. This causes backlight to remain on in the we boot up or resume into a external display only configuration where VBIOS posted on the eDP. [How] Add dpms_off into the condition for

[PATCH 15/20] drm/amd/display: 3.2.15

From: Steven Chiu Signed-off-by: Steven Chiu Reviewed-by: Aric Cyr Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f362b04..8391bc3 100

[PATCH 17/20] drm/amd/display: Poll pending down rep before clear payload allocation table

From: Martin Tsai [Why] On current design, driver cannot handle the interrupt for down reply when link training is processing. The DOWN REQ send before link training will keep in the pending DOWN REP state in the queue. It makes the next DOWN REQ be queued until time out. [How] To add a polling

[PATCH 12/20] drm/amd/display: Adjust ABM 2.2 contrast parameters

From: Josip Pavic [Why] Improved contrast in ABM 2.2 is desired [How] Increase the contrast factor for ABM levels 2, 3 and 4 Signed-off-by: Josip Pavic Reviewed-by: Anthony Koo Acked-by: Leo Li --- drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 6 +++--- 1 file changed, 3 inser

[PATCH 19/20] drm/amd/display: Re-enable CRC capture following modeset

From: Nicholas Kazlauskas [Why] During any modeset the CRTC stream is removed and a new stream is added. This new stream doesn't carry over CRC capture state if it was previously set. [How] Re-program the stream for CRC capture. The existing DRM callback can be re-used here for the most part - t

[PATCH 18/20] drm/amd/display: Enable vblank interrupt during CRC capture

From: Nicholas Kazlauskas [Why] In order to read CRC events when CRC capture is enabled the vblank interrput handler needs to be running for the CRTC. The handler is enabled while there is an active vblank reference. When running IGT tests there will often be no active vblank reference but the t

[PATCH 13/20] revert "drm/amd/display: Add condition to sync eDP SW status and HW status"

From: Eric Yang [Why] This change causes regression for S4 resume where gamma is not programmed. The change incorrectly updates the requested dpms_off state. This reverts commit d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600. Signed-off-by: Eric Yang Reviewed-by: Yongqiang Sun Acked-by: Leo Li ---

[PATCH 20/20] drm/amd/display: Add Vline1 interrupt source to InterruptManager

From: Fatemeh Darbehani [Why] Enhanced sync need to use vertical_interrupt1. [How] Add vertical_interrupt1 source to irq manger, Implment setup vline interrupt interface. Signed-off-by: Fatemeh Darbehani Reviewed-by: Jun Lei Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/core/dc.c

[PATCH 16/20] drm/amd/display: Connect dig_fe to otg directly instead of calling bios

From: hersen wu [Why] After call bios table crtc_source_select, dal will program fmt again. The bios table program dig_source_select and other fmt register for bios usage which is redundancy and uncessary. [How] Program dig_soruce_select register directly Signed-off-by: hersen wu Reviewed-by:

[PATCH 01/35] drm/amd/display: Fix MST reboot/poweroff sequence

From: "Leo (Hanghong) Ma" [Why] drm_dp_mst_topology_mgr_suspend() is added into the new reboot sequence, which disables the UP request at the beginning. Therefore sideband messages are blocked. [How] Finish MST sideband message transaction before UP request is suppressed. Signed-off-by: Leo (Ha

[PATCH 00/35] DC Patches Feb 13, 2019

From: Leo Li Summary of change: * Fix S3 resume black screen on DCE8 * Fix dissapearing cursor on Raven sytems * Cleanup DM plane commit logic * Fixes for multiplane commits * Fixes for seamless boot Anthony Koo (5): drm/amd/display: remove screen flashes on seamless boot drm/amd/display: In

[PATCH 02/35] drm/amd/display: send pipe set command to dmcu when stream unblanks

From: Josip Pavic [Why] When stream is blanked, pipe set command is sent to dmcu to notify it that the abm pipe is disabled. When stream is unblanked, no notification is made to dmcu that the abm pipe has been enabled, resulting in abm not being enabled in the firmware. [How] When stream is unbl

[PATCH 07/35] drm/amd/display: send pipe set command to dmcu when backlight is set

From: Josip Pavic [Why] Previously, a change removed code that would send a pipe set command to dmcu each time the backlight was set, as it was thought to be superfluous. However, it is possible for the backlight to be set before a valid pipe has been set, which causes DMCU to hang after a DPMS r

[PATCH 17/35] drm/amd/display: 3.2.18

From: mmcgarri Signed-off-by: mmcgarri Reviewed-by: Tony Cheng Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1b8eaf5..9adb801 100644

[PATCH 14/35] drm/amd/display: Add disable triple buffering DC debug option

From: Charlene Liu Added a "disable_tri_buf" DC debug option. When set to 1 feature will be off. Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/displ

[PATCH 22/35] drm/amd/display: dcn add check surface in_use

From: Charlene Liu Driver need to poll the SURFACE_INUSE register to determine when to start the new task and write data to the checked surface. Implement the wait functions, and add the necessary hubbub registers. Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Leo Li

[PATCH 11/35] drm/amd/display: Do cursor updates after stream updates

From: Nicholas Kazlauskas [Why] Cursor updates used to happen after vblank/flip/stream updates before the stream update refactor. They now happen before stream updates which means that they're not going to be synced with fb changes and that they're going to programmed for pipes that we're disabli

[PATCH 12/35] drm/amd/display: Clear stream->mode_changed after commit

From: Nicholas Kazlauskas [Why] The stream->mode_changed flag can persist in the following sequence of atomic commits: Commit 1: Enable CRTC0 (mode_changed = true), Enable CRTC1 (mode_changed = true) Commit 2: Disable CRTC1 (mode_changed = false) In this sequence we want to keep the exiting CR

[PATCH 16/35] drm/amd/display: PPLIB Hookup

From: Jun Lei [Why] Make dml and integration with pplib clearer. [How] Change the way the dml formula is initialized to make its values more clear. Restructure DC interface with pplib into rv_funcs. Cap clocks received from pplib. Signed-off-by: Jun Lei Signed-off-by: Eryk Brol Reviewed-by: D

[PATCH 08/35] drm/amd/display: Fix wrong z-order when updating overlay planes

From: Nicholas Kazlauskas [Why] If a commit updates an overlay plane via the legacy plane IOCTL then the only plane in the state will be the overlay plane. Overlay planes need to be added first to the DC context, but in the scenario above the plane will be added last. This will result in wrong z

[PATCH 24/35] drm/amd/display: fix optimize_bandwidth func pointer for dce80

From: Bhawanpreet Lakha [Why] optimize_bandwidth was using dce100_prepare_bandwidth this is incorrect [How] change it to dce100_optimize_bandwidth Signed-off-by: Bhawanpreet Lakha Reviewed-by: Charlene Liu Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h | 4

[PATCH 31/35] drm/amd/display: optionally optimize edp link rate based on timing

From: Josip Pavic [Why] eDP v1.4 allows panels to report link rates other than RBR/HBR/HBR2, that may be more optimal for the panel's timing. Power can be saved by using a link rate closer to the required bandwidth of the panel's timing. [How] Scan the table of reported link rates from the panel

[PATCH 29/35] drm/amd/display: Add p_state_change_support flag to dc_clocks

From: Jun Lei Will be used to signify if P-state change is supported. Signed-off-by: Jun Lei Reviewed-by: Eric Yang Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/

[PATCH 26/35] drm/amd/display: Fix exception from AUX acquire failure

From: Anthony Koo [Why] AUX arbitration occurs between SW and FW components. When AUX acquire fails, it causes engine->ddc to be NULL, which leads to an exception when we try to release the AUX engine. [How] When AUX engine acquire fails, it should return from the function without trying to cont

[PATCH 30/35] drm/amd/display: set clocks to 0 on suspend on dce80

From: Bhawanpreet Lakha [Why] When a dce80 asic was suspended, the clocks were not set to 0. Upon resume, the new clock was compared to the existing clock, they were found to be the same, and so the clock was not set. This resulted in a blackscreen. [How] In atomic commit, check to see if there

[PATCH 28/35] drm/amd/display: Clean up wait on vblank event

From: David Francis [Why] The wait_for_vblank boolean in commit_tail was passed by reference into each stream commit, and if that commit was an asynchronous flip, it would disable vblank waits on all subsequent flips. This made the behaviour depend on crtc order in a non-intuitive way, although

[PATCH 32/35] drm/amd/display: Make stream commits call into DC only once

From: David Francis [Why] dc_commit_updates_for_stream is called twice per stream: once with the flip data and once will all other data. This causes problems when these DC calls have different numbers of planes For example, a commit with a pageflip on plane A and a non-pageflip change on plane B

[PATCH 34/35] drm/amd/display: 3.2.19

From: Mark McGarrity Signed-off-by: Mark McGarrity Reviewed-by: Tony Cheng Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ed11b3c5..eb

[PATCH 04/35] drm/amd/display: Increase precision for backlight curve

From: Anthony Koo [Why] We are currently losing precision when we convert from 16 bit --> 8 bit --> 16 bit. [How] We shouldn't down convert unnecessarily and lose precision. Keep values at 16 bit and use directly. Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Leo Li --- .../drm

[PATCH 15/35] drm/amd/display: Fix negative cursor pos programming

From: Nicholas Kazlauskas [Why] If the cursor pos passed from DM is less than the plane_state->dst_rect top left corner then the unsigned cursor pos wraps around to a large positive number since cursor pos is a u32. There was an attempt to guard against this in hubp1_cursor_set_position by check

[PATCH 33/35] drm/amd/display: Add ability to override bounding box in DC construct

From: Jun Lei Add a dc_bounding_box_overrides struct to define bb overrides. It is loaded in during DC init. Signed-off-by: Jun Lei Reviewed-by: Tony Cheng Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++ drivers/gpu/drm/amd/display/dc/dc.h | 10 ++ 2 files

[PATCH 25/35] drm/amd/display: Reset planes that were disabled in init_pipes

From: Nicholas Kazlauskas [Why] Seamless boot tries to reuse planes that were enabled for the first commit applied. In the case where Raven is booting with two monitors connected and the first commit contains two streams the screen corruption would occur because the second stream was trying to r

[PATCH 19/35] drm/amd/display: Remove redundant 'else' statement in dcn1_update_clocks

From: Fatemeh Darbehani [Why] DM has impelemented new pp_smu interface. 'Else' is not longer needed. Signed-off-by: Fatemeh Darbehani Reviewed-by: Eric Yang Acked-by: Leo Li Acked-by: Yongqiang Sun --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 8 1 file changed, 8 dele

[PATCH 09/35] drm/amd/display: Don't expose support for DRM_FORMAT_RGB888

From: Nicholas Kazlauskas [Why] This format isn't supported in DC and some IGT tests fail since we expose support for it. [How] Remove it. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Harry Wentland Reviewed-by: Leo Li --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file c

[PATCH 35/35] drm/amd/display: Fix issue with link_active state not correct for MST

From: Anthony Koo [Why] For MST, link not disabled until all streams disabled [How] Add check for stream_count before setting link_active = false for MST Signed-off-by: Anthony Koo Reviewed-by: Wenjing Liu Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 +++--

[PATCH 20/35] drm/amd/display: make seamless boot work generically

From: Anthony Koo [Why] Seamless boot code not working on all ASICs because of some underflow issues caused by some uninitialized HW state. [How] Keep some logical and power gating init code in hw_init. Move some per pipe init code to enable accelerated mode Signed-off-by: Anthony Koo Reviewed

[PATCH 10/35] drm/amd/display: Fix update type mismatches in atomic check

From: Nicholas Kazlauskas [Why] Whenever a stream or plane is added or removed from the context the pointer will change from old to new. We set lock and validation needed in these cases. But not all of these cases match update_type from dm_determine_update_type_for_commit - an example being overl

[PATCH 27/35] drm/amd/display: Set flip pending for pipe split

From: Wesley Chalmers [WHY] When doing split pipe, if one pipe is pending on flip, the entire plane's status should be flip pending, otherwise corruption can occur when OS writes to a surface prematurely. [HOW] Clear the flip pending bit before checking pipes, then OR the flip pending bits from

[PATCH 13/35] drm/amd/display: Refactor for setup periodic interrupt.

From: Yongqiang Sun [Why] Current periodic interrupt start point calc in optc is not clear. [How] 1. DM convert delta time to lines number and dc will calculate the start position as per lines number and interrupt type. 2. hwss calculates the start point as per line offset. 3. optc programs v

[PATCH 23/35] drm/amd/display: Allow for plane-less resource reservation

From: Dmytro Laktyushkin This change changes dc add plane logic to allow plane-less resource reservation (pipe split). If a free pipe_ctx (no plane_state attached) is the head pipe, and is found with a bottom pipe attached, assign the plane to add on the bottom pipe. In addition, prepend dcn10

[PATCH 05/35] drm/amd/display: Ungate stream before programming registers

From: Gary Kattan [Why] Certain tests fail after a fresh reboot. This is caused by writing to registers prior to ungating the stream we're trying to program. [How] Make sure the stream is ungated before writing to its registers. This also enables power-gating plane resources before init_hw initi

[PATCH 21/35] drm/amd/display: Add DCN_VM aperture registers

From: Eryk Brol [Why] For later use by the DC VM implementation Signed-off-by: Eryk Brol Reviewed-by: Jun Lei Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/dri

[PATCH 18/35] drm/amd/display: Move enum gamut_remap_select to hw_shared.h

From: Eric Bernstein This enum definition is shared, so move it to a shared location. Signed-off-by: Eric Bernstein Reviewed-by: Tony Cheng Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c| 7 --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 7 --- d

[PATCH 03/35] drm/amd/display: remove screen flashes on seamless boot

From: Anthony Koo [Why] We want boot to desktop to be seamless [How] During init pipes, avoid touching the pipes where GOP has already enabled the HW to the state we want. Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Leo Li --- .../amd/display/dc/dce110/dce110_hw_sequencer.c

[PATCH 06/35] drm/amd/display: Raise dispclk value for dce11

From: Roman Li [Why] The visual corruption due to low display clock value. Observed on Carrizo 4K@60Hz. [How] There was earlier patch for dce_update_clocks: Adding +15% workaround also to to dce11_update_clocks Signed-off-by: Roman Li Reviewed-by: Nicholas Kazlauskas Acked-by: Leo Li --- dr

[PATCH 15/16] drm/amd/display: add i2c over aux failure handling

From: Wenjing Liu [why] We will not retry when EDID read failure using i2c over aux [how] treat i2c over aux failure the same as defer Signed-off-by: Wenjing Liu Reviewed-by: David Francis Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 2 ++ drivers/gpu/drm/amd/display

[PATCH 14/16] drm/amd/display: fix up reference clock abstractions

From: Jun Lei [why] "reference clock" is a very overloaded variable in DC and causes confusion as there are multiple sources of reference clock, which may be different values incorrect input values to DML will cause DCHUB to be programmed improperly and lead to hard to debug underflow issues [ho

[PATCH 03/16] drm/amd/display: Refactor reg_set and reg_update.

From: Yongqiang Sun [Why] Current reg update and reg set use same functions and only delta is update reads reg value and call update function. [How] Refactor reg update and reg set functions. 1.Implement different functions for reg update and reg set. 2.Wrap same process to a help function, both

[PATCH 01/16] drm/amd/display: clean up dml_init_instance

From: Dmytro Laktyushkin Get rid of DV style dml init in favour of the cleaner DC style. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Leo Li --- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- .../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 58 ++

[PATCH 07/16] drm/amd/display: add pipe lock during stream update

From: Wenjing Liu [why] Stream update will adjust both info packets and stream params, need to make sure all things are applied togather. [how] add pipe lock during stream update Signed-off-by: Wenjing Liu Reviewed-by: Jun Lei Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/core/dc.c |

[PATCH 04/16] drm/amd/display: Add PSR SMU Interrupt support

From: SivapiriyanKumarasamy [WHY] We have new bios capabilities enabling s0i2 entry on SMU interrupt. We want this interrupt to be fired on PSR transitions such that we enter s0i2 when entering PSR active. [HOW] Add code to send the SMU interrupt with the appropriate staticscreen flag when enter

[PATCH 02/16] drm/amd/display: Free DCN version of stream encoder

From: Eric Bernstein Cross a TODO item off the list. Cleanup SIGNAL_TYPE_HDMI_FRL, it's not currently supported. Signed-off-by: Eric Bernstein Reviewed-by: Dmytro Laktyushkin Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dcn1

[PATCH 16/16] drm/amd/display: On DCN1, Wait for vupdate on cursor updates

From: David Francis [Why] Cursor updates must acquire the pipe control lock to prevent vupdate from triggering in the middle of cursor programming. On DCN1 the pipe control lock prevents pageflips from occurring. This means that a cursor update right before vupdate can delay a pending pageflip [

[PATCH 06/16] drm/amd/display: Increase DP blank timeout from 30 ms to 50 ms

From: Ken Chalmers [Why] At 24 Hz, a frame is 41.7 ms, so a 30 ms wait can (and does often) timeout. [How] Bump timeout from 30 ms to 50 ms. Signed-off-by: Ken Chalmers Reviewed-by: Tony Cheng Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++-- 1 file

[PATCH 09/16] drm/amd/display: reduce abm min reduction, deviation gain and contrast factor

From: Josip Pavic [Why] Increased power savings are desired for ABM 2.2. [How] Reduce the minimum reduction level, the deviation gain and the contrast factor to allow for more aggressive operation of the algorithm. Signed-off-by: Josip Pavic Reviewed-by: Anthony Koo Acked-by: Leo Li --- dri

[PATCH 11/16] drm/amd/display: implement bounding box update based on uclk breakdown

From: Jun Lei [why] Actual breakdown of DPM level varies by SKU (for the same family) DC needs some ability to ammend pre-silicon numbers Signed-off-by: Jun Lei Reviewed-by: Tony Cheng Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 4 +++- 1 file changed, 3

[PATCH 13/16] drm/amd/display: Expose support for alpha blending on overlays

From: Nicholas Kazlauskas [Why] The DRM overlay planes DM exposes support RGBA formats but are currently forced as fully opaque over whatever they overlay. [How] Expose DRM blending mode and alpha properties to userspace. The overlays exposed support per-pixel pre-multiplied alpha along with gl

[PATCH 05/16] drm/amd/display: Combine field toggle macro and sequence write macro.

From: Yongqiang Sun [Why] field toggle write is actual field sequence write with the same field name. [How] Use REG_UPDATE_SEQ_2 for both sequence write and toggle. Rename REG_UPDATE_1by1_3 to REG_UPDATE_SEQ_3. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Leo Li --- driver

[PATCH 12/16] drm/amd/display: add HW i2c arbitration with dmcu

From: Charlene Liu Signed-off-by: Charlene Liu Reviewed-by: Wenjing Liu Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 12 +++- drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 8 ++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/driver

[PATCH 10/16] drm/amd/display: 3.2.21

From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Leo Li --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e755e2f..9b50536 100644 --

[PATCH 00/16] DC Patches Feb 28, 2019

From: Leo Li Summary of change: * Fix cursor-pageflip interactions on DCN1 * Expose plane alpha-blending support Aric Cyr (1): drm/amd/display: 3.2.21 Charlene Liu (1): drm/amd/display: add HW i2c arbitration with dmcu David Francis (1): drm/amd/display: On DCN1, Wait for vupdate on curs

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