From: Leo Li
[Why]
Idle power states (IPS) describe levels of power-gating within DCN. DM
and DC is responsible for ensuring that we are out of IPS before any DCN
programming happens. Any DCN programming while we're in IPS leads to
undefined behavior (mostly hangs).
Because IPS intersects with
From: Leo Li
[Why]
dc_exit_ips_for_hw_access() is the same as
dc_allow_idle_optimizations(), but with a check on whether IPS is
supported by the ASIC.
[How]
Let's also pipe it through the dm function introduced by the previous
change.
No functional changes are intended.
Signed-off-by: Leo Li
From: Leo Li
[Why]
In preparation for enabling IPS debug flags that require DM changes,
a common entry point for allowing DC idle optimisations is needed.
[How]
Create an alias in DM for dc_allow_idle_optimizations(). Change all
calls to it into dm_allow_idle_optimizations().
No functional ch
From: Leo Li
[Why]
There are currently known backlight and abm issues when IPS is enabled
on DCN35.
While the issues are being ironed out, let's default to
IPS_DISABLE_DYNAMIC so users will not experience hangs. When the issues
are resolved, this patch should be reverted.
[How]
Set the defaul
From: Leo Li
[Why]
The IPS_DISABLE_DYNAMIC configuration disables IPS in all cases except
for when the driver is put into d3 for s0ix.
[How]
Now that we have a common entry point into dc_allow_idle_optimizations
from dm, implement said configuration there.
Signed-off-by: Leo Li
---
.../gpu/
From: Leo Li
[Why]
Idle power states (IPS) describe levels of power-gating within DCN. DM
and DC is responsible for ensuring that we are out of IPS before any DCN
programming happens. Any DCN programming while we're in IPS leads to
undefined behavior (mostly hangs).
Because IPS intersects with
From: Leo Li
[Why]
In preparation for enabling IPS debug flags that require DM changes,
a common entry point for allowing DC idle optimisations is needed.
[How]
Create an alias in DM for dc_allow_idle_optimizations(). Change all
calls to it into dm_allow_idle_optimizations().
No functional ch
From: Leo Li
[Why]
dc_exit_ips_for_hw_access() is the same as
dc_allow_idle_optimizations(), but with a check on whether IPS is
supported by the ASIC.
[How]
Let's also pipe it through the dm function introduced by the previous
change.
No functional changes are intended.
Signed-off-by: Leo Li
From: Leo Li
[Why]
The IPS_DISABLE_DYNAMIC configuration disables IPS in all cases except
for when the driver is put into d3 for s0ix.
[How]
Now that we have a common entry point into dc_allow_idle_optimizations
from dm, implement said configuration there.
Signed-off-by: Leo Li
---
.../gpu/
From: Leo Li
[Why]
There are currently known backlight and abm issues when IPS is enabled
on DCN35.
While the issues are being ironed out, let's default to
IPS_DISABLE_DYNAMIC so users will not experience hangs. When the issues
are resolved, this patch should be reverted.
[How]
Set the defaul
From: Leo Li
[Why]
DCN IPS interoperates with other system idle power features, such as
Zstates.
On DCN35, there is a known issue where system Z8 + DCN IPS2 causes a
hard hang. We observe this on systems where the SBIOS allows Z8.
Though there is a SBIOS fix, there's no guarantee that users wi
From: Leo Li
[Why]
drm_normalize_zpos will set the crtc_state->zpos_changed to 1 if any of
it's assigned planes changes zpos, or is removed/added from it.
To have amdgpu_dm request a plane reset on this is too broad. For
example, if only the cursor plane was moved from one crtc to another,
the
From: Leo Li
[Why]
DC has a special commit path for native cursor, which use the built-in
cursor pipe within DCN planes. This update path does not require all
enabled planes to be added to the list of surface updates sent to DC.
This is not the case for overlay cursor; it uses the same path as
From: Leo Li
These patches aim to make the amdgpgu KMS driver play nicer with compositors
when building multi-plane scanout configurations. They do so by:
1. Making cursor behavior more sensible.
2. Allowing placement of DRM OVERLAY planes underneath the PRIMARY plane for
'underlay' configura
From: Leo Li
[Why]
DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory), to the
other (output encoder).
Each DCN pipe has the ability to blend in a cursor early on in the
pipeline. In other words, there are no dedicate
From: Leo Li
[Why]
Compositors have different ways of assigning surfaces to DRM planes for
render offloading. It may decide between various strategies: overlay,
underlay, or a mix of both
One way for compositors to implement the underlay strategy is to assign
a higher zpos to the DRM_PRIMARY pl
From: Leo Li
To fix CONFIG_ACPI disabled build error.
Fixes: ec6f30c776ad ("drm/amd/display: Set default brightness according to
ACPI")
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/dis
From: Leo Li
To fix CONFIG_ACPI disabled build error.
v2: Instead of ifdef-ing inside function, define a no-op stub for
amdgpu_acpi_get_backlight_caps when CONFIG_ACPI=n
Fixes: ec6f30c776ad ("drm/amd/display: Set default brightness according to
ACPI")
Signed-off-by: Leo Li
---
drivers/gpu/dr
From: Leo Li
This change caused PSR SU panels to not read from their remote fb,
preventing us from entering self-refresh. It is a regression.
This reverts commit f8ebe6341a6a3745ef02648b4b5c2c89fa4a9ace.
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 -
1 file
From: Leo Li
[Why]
DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory), to the
other (output encoder).
Each DCN pipe has the ability to blend in a cursor early on in the
pipeline. In other words, there are no dedicate
From: Leo Li
[Why]
Compositors have different ways of assigning surfaces to DRM planes for
render offloading. It may decide between various strategies: overlay,
underlay, or a mix of both (see here for more info:
https://gitlab.freedesktop.org/emersion/libliftoff/-/issues/76)
One way for compos
From: Leo Li
eDP 1.5 specification defines PSR version 4.
It defines PSR1 and PSR2 support with selective-update (SU)
capabilities, with additional support for Y-coordinate and Early
Transport of the selective-update region.
This differs from PSR version 3 in that early transport is supported
f
From: Leo Li
[Why]
Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we observe that with PSR SU, it causes
visual artifacts, higher power usage, and potential system hang.
Thi
From: Leo Li
On ChromeOS clang build, the following warning is seen:
/mnt/host/source/src/third_party/kernel/v5.15/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:463:6:
error: variable 'mc_umc_status' is used uninitialized whenever 'if' condition
is false [-Werror,-Wsometimes-uninitialized]
if
From: Leo Li
[Why]
Enabling Z10 optimizations allows DMUB to disable the OTG during PSR
link-off. This theoretically saves power by putting more of the display
hardware to sleep. However, we observe that with PSR SU, it causes
visual artifacts, higher power usage, and potential system hang.
Thi
From: Leo Li
DC_FP_START/END is only defined for CONFIG_DRM_AMD_DC_DCN enabled
builds, and update_bw_bounding_box() is only valid for DCN ASICs.
Therefore, wrap the entire thing in the ifdef guard.
Acked-by: Alex Deucher
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2
From: Leo Li
[Why]
During DC init, we read power management tables from PMFW. This info is
exchanged in the form of a binary blob inside gpu memory. In order to
parse the binary blob, the correct struct needs to be used.
[How]
Fix dcn316's definition of the DfPstateTable_t struct to align with
From: Leo Li
[Why]
Being able to configure visual confirm at boot or in cmdline is helpful
when debugging.
[How]
Add a module parameter to configure DC visual confirm, which works the
same way as the equivalent debugfs entry.
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
From: Leo Li
[Why & How]
It's useful to disable MPO when debugging or testing. Therefore, add a
dcdebugmask option to disable MPO.
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
2 files changed, 5
From: Leo Li
When pinning a buffer, we should check to see if there are any
additional restrictions imposed by bo->preferred_domains. This will
prevent the BO from being moved to an invalid domain when pinning.
For example, this can happen if the user requests to create a BO in GTT
domain for di
From: Leo Li
When pinning a buffer, we should check to see if there are any
additional restrictions imposed by bo->preferred_domains. This will
prevent the BO from being moved to an invalid domain when pinning.
For example, this can happen if the user requests to create a BO in GTT
domain for di
From: Leo Li
[Why]
drm_atomic_normalize_zpos() can return an error code when there's
modeset lock contention. This was being ignored.
[How]
Bail out of atomic check if normalize_zpos() returns an error.
Fixes: b261509952bc ("drm/amd/display: Fix double cursor on non-video RGB MPO")
Signed-off
From: Leo Li
The first two patches here add PSR SU Rate Control support to DC. Support in
amdgpu_dm is still pending to enable this fully.
The last two patches are some fixes for PSR SU.
David Zhang (3):
drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support
drm/amd/display: Add PS
From: David Zhang
[why & how]
Expose vendor specific DPCD registers for rate controlling the eDP sink
TCON's refresh rate during PSR active. When used in combination with
PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for
short.
v2: Add all DPCD registers required
Signed-
From: David Zhang
[Why]
PSR-SU Rate Control - or PSR-SU-RC - enables PSR-SU panels to work with
variable refresh rate to allow for more power savings. Lowering the
refresh rate can increase PSR residency by expanding the eDP main link
shut down duration. It can also lower panel power consumption
From: David Zhang
[why]
DMUB FW uses OTG instance to get eDP panel instance. But in case
of MPO multiple pipe indexes are passed to updated the same panel.
The other OTG instance passed would be ignored causing in DMUB not
acknowledging the messages.
[how]
Add panel instance to dirty rectangle d
From: Robin Chen
[Why]
To wrap the decision logic of sending dirty rect dmub command
for both frame update and cursor update path.
Signed-off-by: Robin Chen
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 14 ++-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24
From: David Zhang
[Why]
In cases where there are multiple eDP instances, DMUB needs to know
which instance the command is for. Today, the field for specifying the
panel_inst exists in both dmub_cmd_update_dirty_rect_data and
dmub_cmd_update_cursor_info_data.
For cursor updates, we already speci
From: Leo Li
[Why]
There is a theoretical problem in prior patches for reducing the stack
size of *update_bw_bounding_box() functions.
By modifying the soc.clock_limits[n] struct directly, this can cause
unintended behavior as the for loop attempts to swap rows in
clock_limits[n]. A temporary s
From: Leo Li
This series has dependencies on the recent Renoir series:
https://patchwork.freedesktop.org/series/67803/#rev2
Summary of changes:
* Enable PSR on supported eDP panels
* Allow programming of negative gamma slope
Aidan Yang (2):
drm/amd/display: Don't use optimized gamma22 with e
From: Jun Lei
Signed-off-by: Jun Lei
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
b/drivers/gpu/dr
From: Jun Lei
[why]
Hard to determine if pipe combine is done with MPC or ODM
[how]
Add new visual confirm type, this will mark each MPCC tree
with a different color
Signed-off-by: Jun Lei
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
From: Aidan Yang
[why]
Optimized gamma22 assumes fixed point distribution which is not true
for eetf true.
[how]
Use long calculation for eetf.
Signed-off-by: Aidan Yang
Reviewed-by: Krunoslav Kovac
Acked-by: Leo Li
Acked-by: Reza Amini
---
.../amd/display/modules/color/color_gamma.c | 4
From: Dmytro Laktyushkin
This value will be needed by dml and therefore should be externally
accessible.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nevenko Stupar
Acked-by: Leo Li
---
.../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c| 14 +++---
.../amd/display/dc/clk_mgr/dce11
From: Jordan Lazare
[Why]
For loop below the assert already checks for the number of instances to
create. ASSERT is meaningless and causing spam.
[How]
dd
Signed-off-by: Jordan Lazare
Reviewed-by: Harry Wentland
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2
From: Roman Li
[Why]
For upcoming PSR stupport it's useful to have debug entry
to verify psr state.
[How]
- Enable psr dc api for Linux
- Add psr_state file to eDP connector debugfs
usage e.g.: cat /sys/kernel/debug/dri/0/DP-1/psr_state
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauska
From: Aidan Yang
[why]
There's a use case for inverted gamma
and it's been confirmed that negative slopes are ok.
[how]
Remove code for blocking non-monotonically increasing gamma
Signed-off-by: Aidan Yang
Reviewed-by: Krunoslav Kovac
Acked-by: Leo Li
Acked-by: Reza Amini
---
.../amd/displ
From: Yongqiang Sun
[Why]
System hang during S0i3 if DP only connected due to clk is disabled when
doing link training.
During S0i3, clk is disabled while the clk state is updated when ini_hw
called, and at the moment clk is still disabled which indicating a wrong
state for next time trying to en
From: Anthony Koo
[Why]
In diags environment we are not programming the DPP DTO
correctly.
[How]
Populate the dpp refclk in dccg so it can be used to correctly
program DPP DTO.
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
.../drm/amd/display/dc/clk_mgr/dcn20/dcn20
From: Michael Strauss
[WHY]
i2c_read is called to differentiate passive DP->HDMI and DP->DVI-D dongles
The call is expected to fail in DVI-D case but pass in HDMI case
Some HDMI dongles have a chance to fail as well, causing misdetection as DVI-D
[HOW]
Retry i2c_read to ensure failed result is v
From: Jun Lei
[why]
SLT tests require that diag can drive eDP even if nothing is connected, this is
not
typical production use case, so we need to add flag
[how]
add flag, and this flag supercedes "should destroy" logic
Signed-off-by: Jun Lei
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
driv
From: Michael Strauss
[WHY]
force_single_disp_pipe_split is a debug flag for use on DCN1
but isn't necessary otherwise as DCN2+ splits by default
Signed-off-by: Michael Strauss
Reviewed-by: Tony Cheng
Acked-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_res
From: Yongqiang Sun
[Why & How]
vm should be enabled by default for rn to get
right dml.
Signed-off-by: Yongqiang Sun
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 29 ---
1 file changed, 25 inser
From: Dmytro Laktyushkin
These are specific to dcn21 and should not be increased for
reuse on other asics.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Chris Park
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Alvin Lee
[Why]
NV12 has lower min dcfclk
[How]
Add update in update_bounding_box
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c| 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/dr
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Chris Park
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drive
From: Yogesh Mohan Marimuthu
[Why]
The enum value for TRANSMITTER_UNIPHY_G is 9. In resource dc_xx_resource
file structure link_enc_regs[], the TRANSMITTER_UNIPHY_G registers are
initialized at index 6. Due to this mismatch, if monitor is attached to
port using TRANSMITTER_UNIPHY_G then the monit
From: Eric Yang
[Why]
SMU does not keep the wm table across S3, S4, need to re-send
the table. Also defer sending the cable to after DCN bave initialized
[How]
Send table at end of init hw
Signed-off-by: Eric Yang
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
.../amd/display/dc/clk_mgr/dc
From: Noah Abradjian
[Why]
* Clk Mgr DTO update point did not cover all needed updates, as it included a
check for plane_state which does not exist yet when the updater is called on
driver startup
* This resulted in another update path in the pipe programming sequence, based
on a dppclk up
From: Reza Amini
[why]
We want to use maximum space on display to show source
[how]
For Centered Mode: Replicate source as many times as possible to use
maximum of display active space add borders.
Signed-off-by: Reza Amini
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
.../gpu/drm/amd/displ
From: Lewis Huang
[Why]
Signal is update to EDP when driver disable first encoder. The
following encoder using SIGNAL_TYPE_EDP to handle other
device. When encoder signal is HDMI, driver will detect it is dp
and release phy. It cause hw hang.
[How]
Take signal type from link->connector_signal.
From: Dmytro Laktyushkin
One of odm variables was not initialized in dml.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Chris Park
Acked-by: Leo Li
Acked-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h |
From: Sung Lee
[Why]
In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP.
This causes an issue on dc init where dcn2_1_soc which has been
updated by update_bw_bounding_box gets put into dml->soc.
As update_bw_bounding_box is currently incorrect for dcn2.1,
this makes dml calculations fa
From: Eric Yang
[Why]
Fix the programming of DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A.
Was not filled in.
Signed-off-by: Eric Yang
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_reso
From: Dmytro Laktyushkin
We are currently incorrectly processing avoid split at highest
voltage level.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 11 +++
1 file changed, 7 insertions(+), 4
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2e1d34882684..a86dad3808b6 100644
--- a/drivers/g
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 1 +
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
From: Michael Strauss
[WHY]
DML is incorrectly initialized with 4 pipes on 3 pipe configs
RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe
case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display)
[HOW]
Set correct number of DPP/OTGs for dml init to
From: Anthony Koo
[Why]
When aux engine acquire fails, we missed populating the operation_result
that describes the failure reason.
[How]
Set operation_result to new type:
AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE
in the case aux engine acquire has failed.
Signed-off-by: Anthony Koo
Reviewed
From: Roman Li
[Why]
PSR (Panel Self-Refresh) is a power-saving feature for eDP panels.
The feature has support in DMCU (Display MicroController Unit).
DMCU/driver communication is implemented in DC.
DM can use existing DC PSR interface to use PSR feature.
[How]
- Read psr caps via dpcd
- Send v
From: Dmytro Laktyushkin
Commit hints are unnecessary after front end programming redesign.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 --
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c |
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index b578b2148e45..0416a17b0897 100644
--- a/drivers/g
From: Joshua Aberback
[Why]
This workaround was put in dcn2 DMLv1, and now we need it in DMLv2.
Signed-off-by: Joshua Aberback
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
dif
From: Krunoslav Kovac
[Why&How]
BT.2390 EETF is used for tone mapping/range reduction.
Say display is 0.1 - 500 nits.
The problematic case is when content is 0-400. We apply EETF because
0<0.1 so we need to reduce the range by 0.1.
In the commit, we ignore the bottom range. Most displays map 0 t
From: Jun Lei
[why]
A display that supports DRR can never really be considered
"synchronized" with any other display because we can dynamically
enable DRR (i.e. without modeset). this will cause their
relative CRTC positions to drift and lose sync. this will disrupt
features such as MCLK switch
From: Paul Hsieh
[Why]
On some systems, we need to check the dcn version in runtime
system, not in compile time.
[How]
Stub in dcn version parameter to find_first_free_audio
Signed-off-by: Paul Hsieh
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_resou
From: Dmytro Laktyushkin
Split a large function into smaller, reusable chunks.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nevenko Stupar
Acked-by: Leo Li
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 182 ++
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 31 +++
.
From: Leo Li
[Why]
Some LED panel drivers might not like fractional PWM. In such cases,
backlight flickering may be observed.
[How]
Add a DC feature mask to disable fractional PWM, and associate it with
the preexisting dc_config flag.
The flag is only plumbed through the dmcu firmware, so plu
From: Leo Li
[Why]
Some LED panel drivers might not like fractional PWM. In such cases,
backlight flickering may be observed.
[How]
Add a DC feature mask to disable fractional PWM, and associate it with
the preexisting dc_config flag.
The flag is only plumbed through the dmcu firmware, so plu
From: Leo Li
[Why]
For DCN hardware, the crtc_high_irq handler is assigned to the vstartup
interrupt. This is different from DCE, which has it assigned to vblank
start.
We'd like to send vblank and user events at vstartup because:
* It happens close enough to vupdate - the point of no return f
From: Leo Li
[Why]
On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
handler redundant.
All the vupdate handler does is handle vblank events, and update vrr
for DCE hw (excluding VEGA, more on that later). As far as usermode is
concerned. vstartup happens close enough to vupdate
From: Leo Li
[Why]
On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
handler redundant.
All the vupdate handler does is handle vblank events, and update vrr
for DCE hw (excluding VEGA, more on that later). As far as usermode is
concerned. vstartup happens close enough to vupdate
From: Leo Li
[Why]
On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
handler redundant.
All the vupdate handler does is handle vblank events, and update vrr
for DCE hw (excluding VEGA, more on that later). As far as usermode is
concerned. vstartup happens close enough to vupdate
From: Leo Li
[Why]
On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
handler redundant.
All the vupdate handler does is handle vblank events, and update vrr
for DCE hw (excluding VEGA, more on that later). As far as usermode is
concerned. vstartup happens close enough to vupdate
From: Leo Li
Summary of change:
* Edid emulation fix
* S3 resume fix on Vega10
* Add build types for internal tracking
* Fix screen corruption on polaris
* Interlace video timing fix
Bhawanpreet Lakha (1):
drm/amd/display: Fix Edid emulation for linux
Charlene Liu (2):
drm/amd/display: fix
From: Jun Lei
[why]
Sometimes there are indications that the incorrect driver is being
loaded in automated tests. This change adds the ability for builds to
be tagged with a string, and picked up by the test infrastructure.
[how]
dc.c will allocate const for build id, which is init-ed with defau
From: Charlene Liu
[Why]
HDMI_scramber is not enabled for pixel rate >340Mhz.
[How]
Calculate the phy clock to include the Hw frame packing factor.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
1 file chang
From: Nikola Cornij
[why]
Same functions exist for all other signal types.
[how]
Add a function that checks against virtual signal type.
Signed-off-by: Nikola Cornij
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/include/signal_types.h | 5 +
1 file changed, 5 insertions(+)
diff --
From: Su Sung Chung
[Why]
Previously bandwidth validation was failing because swizzle mode was not
initialized during plane_state allocation. The swizzle mode was
calculated using pixed format which is how swizzle mode is initially
calculated in addrlib.
[How]
* Set default swizzle mode for vali
From: Eryk Brol
Also add dram clock to clocks struct, for systems that uses them.
Signed-off-by: Eryk Brol
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +
drivers/gpu/drm/amd/display/dc/dc.h | 4 +++-
drivers/gpu/drm/amd/display/
From: Eric Yang
[why]
Currently not supported, will black screen when set.
[How]
Fail validate timing helper for those modes.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 3 +++
drivers/gpu/drm/amd/display/
From: Eric Yang
[Why]
All ASICS we support has YCbCr support, so
the check is unnecessary, the currently logic
in validate output also returns true all
the time, so the unneccessary logic is removed
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/dis
From: Jun Lei
[why]
ddc engines were recently changed to be independently tracked
from pipe count. the change was reflected in resource constructor
but not in destructor. this manifests as a memory leak when
pipe harvesting is enabled, since not all constructed ddc engines
are freed
[how]
make
From: Yongqiang Sun
[Why]
DF keeps awake after S0i3 resume due to DRAM_STATE_CNTL
is set by bios command table during dcn init_hw.
[How]
As a work around, check STATE_CNTL status before init_hw,
if it is 0 before init_hw and set to 1 after init_hw,
change it to 0.
Signed-off-by: Yongqiang Sun
From: Bhawanpreet Lakha
[Why]
EDID emulation didn't work properly for linux, as we stop programming
if nothing is connected physically.
[How]
We get a flag from DRM when we want to do edid emulation. We check if
this flag is true and nothing is connected physically, if so we only
program the fro
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Steven Chiu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f328483..1995271 10
From: Charlene Liu
[Description] interlace mode shows wrong vertical timing.
Interface timing in Edid is half vertical timing as progressive timing.
driver doubled the vertical timing in edid_paser,
no need to double in optc again.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by:
From: Leo Li
[Why]
There is no reason why the common data needs to be kept separate.
[How]
Flatten the struct by moving common data into the DM IRQ struct.
Signed-off-by: Leo Li
Reviewed-by: David Francis
Acked-by: Leo Li
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 37 -
From: Murton Liu
[Why]
Due to a small pre-fetch window, the active vline timing is a couple
of lines off when compared to what it should be.
[How]
Changed the calculation for the start vline to account for this window.
Signed-off-by: Murton Liu
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
dri
From: Roman Li
[Why]
There have been a few reports of Vega10 display remaining blank
after S3 resume. The regression is caused by workaround for mode
change on Vega10 - skip set_bandwidth if stream count is 0.
As a result we skipped dispclk reset on suspend, thus on resume
we may skip the clock u
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