[PATCH] drm/amdkfd: Correct the value of the no_atomic_fw_version variable

IP_VERSION(10, 3, 5) yellow_carp IP_VERSION(10, 3, 3) Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index

[PATCH] drm/amdgpu: When the VCN(1.0) block is suspended, powergating is explicitly enabled

change the power state flag of the vcn block to POWER_STATE_OFF. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index d54d720..d73676b 10

[PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function

Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 +- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 024460b..d7e9a18 100644 --- a/drivers

[PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function

case we enable this code in the future. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 +- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index

[PATCH] drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven

cy" when gfxoff. [How] Disable gfxoff when setting manual mode. By the way, from the user point of view, now that user switch to manual mode and force SCLK Frequency, he don't want SCLK be controlled by workload. It becomes meaningless to "switch to manual mode" if APU enter &qu

[PATCH] drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven

force SCLK Frequency, he don't want SCLK be controlled by workload.It becomes meaningless to "switch to manual mode" if APU enter "gfxoff" due to lack of workload at this point. Tips: Same issue observed on Raven. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu

[PATCH] drm/amd/smu: correct a mistake

Corresponding to smu_workload_get_type(smu, type) is "get_workload_type" Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd

[PATCH] drm/amdgpu/powerplay: Target power profile mode should be the second parameter of renoir_set_power_profile_mode

A small mistake Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index f286c1e..ae87c46 100644 --- a/drivers

[PATCH] drm/amdgpu/powerplay: Modify SMC message name for setting power profile mode

I consulted Cai Land(chuntian@amd.com), he told me corresponding smc message name to fSMC_MSG_SetWorkloadMask() is "PPSMC_MSG_ActiveProcessNotify" in firmware code of Renoir. Strange though it may seem, but it's a fact. Signed-off-by: chen gong --- drivers/gpu/dr

[PATCH] drm/amdgpu: do not enable asic reset for raven2

The GPU reset function of raven2 is not maintained or tested, so it should be very unstable. Now the amdgpu_asic_reset function is added to amdgpu_pmops_suspend, which causes the S3 test of raven2 to fail, so the asic_reset of raven2 is ignored here. Signed-off-by: Chen Gong --- drivers/gpu

[PATCH] drm/amdgpu/psp: declare PSP TA firmware

Add PSP TA firmware declaration for raven raven2 picasso Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index b96484a..b345e69 100644

[PATCH] drm/amdgpu: Fix SDMA hang when performing VKexample test

VKexample test hang during Occlusion/SDMA/Varia runs. Clear XNACK_WATERMK in reg SDMA0_UTCL1_WATERMK to fix this issue. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu

[PATCH] drm/amd/powerplay: modify the parameters of SMU_MSG_PowerUpVcn to 0

The parameters what SMU_MSG_PowerUpVcn need is 0, not 1 Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c index

[PATCH] drm/amdgpu/powerplay: add one flag to show that no one message be sent yet by SMU

The value of the register mmMP1_SMN_C2PMSG_90 should be 0 when initializing smu and after resuming smu. Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 ++- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/powerplay/smu_v12_0.c

[PATCH] drm/amd/powerplay: Disable gfx CGPG when suspend smu

message 0x2f,response 0xfffb param 0x1 [ 151.844605 ] amdgpu: [powerplay] SMU is resumed successfully! Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd

[PATCH] drm/amdgpu: disable page queue on SDMA for Vega12

From: Junwei Zhang It blocks most of sanity tests, so disable it for now. Tested-by: Chen Gong Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu

[PATCH] drm/amdgpu: Need to power up SDMA for #34 sdma firmware after do mode2 reset on Renoir

power. Then I re-enable function "amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false)" during mode2 reset, The result is issue disappear. Besides, I did more experiments base on previous sdma firmware for this patch. Situation Normal. [how] Remove "!adev->in_gpu_reset" S

[PATCH 2/2] drm/amdgpu: reading CP_MEM_SLP_CNTL register using RREG32_KIQ macro

Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to hang when GPU is in "gfxoff" state. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/d

[PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32

Reading some registers by mmio will result in hang when GPU is in "gfxoff" state. This problem can be solved by GPU in "ring command packages" way. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_devi

[PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ

Move amdgpu_virt_kiq_rreg function to amdgpu_device.c, and rename it to amdgpu_kiq_rreg.Make it generic and flexible。 Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 +- drivers/gpu/drm

[PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro

Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to hang when GPU is in "gfxoff" state. I do a uniform substitution here. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32

Reading some registers by mmio will result in hang when GPU is in "gfxoff" state. This problem can be solved by GPU in "ring command packages" way. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_devi

[PATCH 3/3] drm/amdgpu: read gfx register using RREG32_KIQ macro

Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to hang when GPU is in "gfxoff" state. I do a uniform substitution here. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[PATCH 1/3] drm/amdgpu: provide a generic function interface for reading register by KIQ

Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c, and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and flexible. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 96

[PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32

Reading some registers by mmio will result in hang when GPU is in "gfxoff" state.This problem can be solved by GPU in "ring command packages" way. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 drivers/gpu/drm/amd/amdgpu/amdgpu_device

[PATCH 2/3] drm/amdgpu: add kiq version interface for RREG32/WREG32

Reading some registers by mmio will result in hang when GPU is in "gfxoff" state.This problem can be solved by GPU in "ring command packages" way. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 drivers/gpu/drm/amd/amdgpu/amdgpu_device

[PATCH 1/3] drm/amdgpu: provide a generic function interface for reading/writing register by KIQ

Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c, and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and flexible. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 96

[PATCH 3/3] drm/amdgpu: read gfx register using RREG32_KIQ macro

Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to hang when GPU is in "gfxoff" state. I do a uniform substitution here. Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU RESET

" to skip function "smu_feature_is_enabled". Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 - drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 6 ++ 3 files changed, 13 insertions(+), 1 dele

[PATCH 2/2] drm/amdgpu: Use mode2 mode to perform GPU RESET for Renoir

Signed-off-by: chen gong --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 58818761..0f639df9 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd

[PATCH] drm/amdgpu: Do not implement power-on for SDMA after do mode2 reset on Renoir

Find that ring sdma0 test failed if turn on SDMA powergating after do mode2 reset. Perhaps the mode2 reset does not reset the SDMA PG state, SDMA is already powered up so there is no need to ask the SMU to power it up again. So I skip this function for a moment. Signed-off-by: chen gong

[PATCH] drm/amdgpu: No need to check gfxoff status after enable gfxoff feature

smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch. As to when GPU get into "GFXoff" will be up to drawing load. So we can not sure which state GPU should be in after enable gfxoff feature. Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 9 --