one completion doesn't need to worry about interruption
from signal.
Signed-off-by: Stylon Wang
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DC v3.2.135.1
* Improvements across DP, DPP, clock management, pixel formats
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.65
Anthony Wang (1):
drm/amd/display: Handle potential dpp_inst mismat
From: Jimmy Kizito
[Why]
Some extra provisions are required during DPRX detection for links which
lack physical HPD and AUX/DDC pins.
[How]
Avoid attempting to access nonexistent physical pins during DPRX
detection.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
From: Jimmy Kizito
[Why]
Some links are dynamically assigned link encoders on stream enablement.
[How]
Update DisplayPort training parameter determination stage that assumes
link encoder statically assigned to link.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 ++-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 40 +++
.../drm/amd/display/dc/core/dc_link_hwss.c| 3 +-
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 3 +-
.../amd/display/include
From: Jimmy Kizito
[Why & How]
Add functionality useful for DP link training to public interface.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 +-
drivers/gpu/drm/amd/display/dc/inc/dc_link_
From: Fangzhi Zuo
Signed-off-by: Fangzhi Zuo
Reviewed-by: Mikita Lipski
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b
variables like DETBufferSizeY,
DETBufferSizeC that are involved in DETBufferSizeInKByte calculations
to unsigned int in all the display_mode_vba_xx files.
Signed-off-by: Chaitanya Dhere
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../dc/dml/dcn20/display_mode_vba_20.c| 26
link_service_types.h
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 124 ++
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_link.h | 6 -
.../amd/display/include
per DCFCLK level instead of one entry
per FCLK level. This is needed because the maximum FCLK does not
necessarily need maximum voltage, whereas DCFCLK values from SMU
cover the full voltage range.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../amd
: Hanghong Ma
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 27c5d49a7bc1
the dpp_inst
associated with each pipe from res_pool.
Signed-off-by: Anthony Wang
Reviewed-by: Yongqiang Sun
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display
From: Dmytro Laktyushkin
Right now the flag simply selects memory config 0 when flag is true
however 420 modes benefit more from memory config 3.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 9
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index d9e1657ba6a6
From: Anthony Koo
- Implement INBOX0 messaging for HW lock
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 123 +-
1 file changed, 116 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
From: Aric Cyr
- adding missed FW promotion
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DC v3.2.136
* Improvements across DP, DMUB, code documentation, suspend/resume, etc
--
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.66
Aric Cyr (1):
drm/amd/display: 3.2.136
Bhawanpreet Lakh
Reviewed-by: Sung Lee
Acked-by: Stylon Wang
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 48 ++-
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b
From: Wyatt Wood
[Why]
Need to get current DMUB time.
[How]
Add get_current_time interface to dmub_srv.
Signed-off-by: Wyatt Wood
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++-
.../gpu/drm/amd/display/dc/dcn21
From: Rodrigo Siqueira
This commit introduces kernel documentation to some essential functions
related to power gate control over planes. It also adds a macro to make
one part of the code easy to understand.
Signed-off-by: Rodrigo Siqueira
Reviewed-by: Harry Wentland
Acked-by: Stylon Wang
Wentland
Acked-by: Stylon Wang
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 160 --
1 file changed, 160 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 90cd8f8529d3
From: Rodrigo Siqueira
Signed-off-by: Rodrigo Siqueira
Reviewed-by: Harry Wentland
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
b/drivers/gpu
in
order to make it easy for developers to navigate this set of functions.
Signed-off-by: Rodrigo Siqueira
Reviewed-by: Harry Wentland
Acked-by: Stylon Wang
---
.../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 49 +--
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 6 +++
2
From: George Shen
[Why]
Improve readability and maintainability of code.
[How]
Refactor test pattern size calculation out of function
call parameter and store value in variable.
Signed-off-by: George Shen
Reviewed-by: Wenjing Liu
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core
,
disconnect sink on detection when no EDID
is read due to timeout.
Signed-off-by: Chris Park
Reviewed-by: Nicholas Kazlauskas
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd
From: Wenjing Liu
[how]
Implement a function that determines link encoding format
based on the link settings passed in.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++
drivers/gpu/drm/amd/display/dc
From: Wenjing Liu
[how]
Rename initialize_training_settings to decide_training_settings.
Call get link encoding format and decide training settings
based on current channel coding.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core
erstand it.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/displ
From: Wenjing Liu
[why]
Some lttpr configuration steps are exclusive to 8b/10b channel
coding mode. We need to take channel conding into account.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Stylon Wang
Acked-by: Wesley Chalmers
---
.../gpu/drm/amd/display/dc/core
Wayne Lin
Reviewed-by: Chao-kai Wang
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 61 ---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 4 --
3 files changed, 15 insertions(+), 77 dele
are the stutter_period with the frame time and if we will overflow
there is no point in trying to enable MALL (and see the ASSERT) so we
early exist in this case
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
From: Zhan Liu
[Why]
eDP version and DPCD revision are different. Per VESA
spec, "The DPCD revision for eDP v1.4 is 13h".
SUPPORTED_LINK_RATES is valid since eDP v1.4 (DPCD_REV_13).
[How]
Correct DPCD_REV for eDP v1.4.
Signed-off-by: Zhan Liu
Reviewed-by: Nikola Cornij
Acked-by: S
EINVAL to skip actions on vblank refcount when stream is not
enabled.
Signed-off-by: Wayne Lin
Reviewed-by: Chao-kai Wang
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +-
2 files changed, 4
igned-off-by: Nikola Cornij
Reviewed-by: Charlene Liu
Reviewed-by: Harry Wentland
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 7 ---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 7 ---
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resou
for driver flips, visual confirm
needs to be updated on every frame, including fast updates.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.
Signed-off-by: Wyatt Wood
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
.../amd/display/dc
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 63b61468898f
This DC patchset brings improvements in multiple areas. In summary, we have:
- DC refactor and bug fixes for DP links
- Bug fixes for DP2
- Fix regressions causing display not light up
- Improved debug trace
- Improved DP AUX transfer
- Updated watermark latencies to fix underflows in some modes
From: "Shen, George"
[Why]
Certain configurations will result in link encoder
to not be assigned to the link at the time we apply
cable ID logic. We should skip it in those cases.
[How]
Check if link_enc is not null before applying
cable ID.
Reviewed-by: Wenjing Liu
Acked-by: S
From: Wyatt Wood
[Why + How]
Payload reply is unknown and not handled in switch statement.
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
From: Paul Hsieh
[Why]
The original latencies were causing underflow in some modes.
Resolution: 2880x1620@60p when HDR enable
[How]
1. Replace with the up-to-date watermark values based on new measurments
2. Correct the ddr_wm_table name to DDR5 on DCN31
Reviewed-by: Aric Cyr
Acked-by: Stylon
From: "Leo (Hanghong) Ma"
[Why]
We find some of the driver sequence debug trace for infoframe
update is missing so add it.
[How]
Add the missing sequence debug trace for infoframe update.
Reviewed-by: Martin Leung
Acked-by: Stylon Wang
Signed-off-by: Leo (Hanghong) Ma
---
drive
From: Zhan Liu
[Why]
This change causes regression, that prevents some systems
from lighting up internal displays.
[How]
Revert this patch until a new solution is ready.
Reviewed-by: Charlene Liu
Acked-by: Stylon Wang
Signed-off-by: Zhan Liu
---
.../amd/display/dc/dce110
From: Wenjing Liu
[why]
Factor setup/reset stream encoder to link hwss.
Acked-by: Wayne Lin
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 64 +++
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 23 +--
.../drm/amd/display/dc/core/dc_link_hwss.c| 170
From: Wenjing Liu
[how]
1. move decide det link training link resource before each link training.
2. move disable link for handling vbios case into set all streams
dpms off for link sequence.
3. extract usbc hotplug workaround into its own wa function.
4. Minor syntax changes to improve code read
From: Wenjing Liu
[why]
Factor enable/disable dp link output to link hwss.
Acked-by: Wayne Lin
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-
.../drm/amd/display/dc/core/dc_link_hwss.c| 256 +-
.../gpu/drm/amd/display/dc/inc/link_hws
From: Wenjing Liu
[why]
Factor set dp link test pattern to link_hwss.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/core/dc_link_hwss.c| 46 +++
.../gpu/drm/amd/display/dc/inc/link_hwss.h| 3 ++
2 files changed, 29
From: Wenjing Liu
[why]
Factor set dp lane settings to link_hwss.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/core/dc_link_hwss.c| 40 ++-
.../drm/amd/display/dc/dce/dce_link_encoder.c | 17
.../drm/amd
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 613
.../drm/amd/display/dc/core/dc_link_hwss.c| 653 +-
drivers/gpu/drm/amd/display/dc/dc_link.h | 4 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c
From: Wenjing Liu
[why]
Isolate the way to obtain link_hwss from the actual implemenation
of link_hwss. So the caller can call link_hwss without knowing
the implementation detail of link_hwss.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc
From: Wenjing Liu
[why]
Move link_hwss to its own folder as part of DC LIB and break it down
to separate file one for each type of backend for code isolation.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/Makefile | 4
From: Anthony Koo
- Correct number of reserved bits in cmd_lock_hw
- Extend bits of hw_lock_client to allow for more clients
Acked-by: Stylon Wang
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 8
1 file changed, 4 insertions(+), 4 deletions
From: Fangzhi Zuo
DP2 sequence is triggered only if VESA certified cable is detected.
Force DP2 sequence with uncertified cable for testing purpose.
Reviewed-by: Wenjing Liu
Acked-by: Stylon Wang
Signed-off-by: Fangzhi Zuo
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 26
From: Aric Cyr
This version brings along following fixes:
- DC refactor and bug fixes for DP links
- Bug fixes for DP2
- Fix regressions causing display not light up
- Improved debug trace
- Improved DP AUX transfer
- Updated watermark latencies to fix underflows in some modes
Acked-by: Stylon
s that hook, and that causes null ptr hang.
Signed-off-by: Fangzhi Zuo
Acked-by: Stylon Wang
---
.../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c| 11 +++
.../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h| 9 ++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff -
visual confirm to updated independently
of MPCC blending updates.
Signed-off-by: Wyatt Wood
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 98
.../display/dc/dce110/dce110_hw_sequencer.c | 35 --
.../amd/display/dc/dcn10
-by: Aric Cyr
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index e0badab84
From: Po-Ting Chen
[Why]
To support a new visual confirm mode: swizzle to show the specific
color at the screen border according to different surface swizzle mode.
Currently we only support the Linear mode with red color.
Signed-off-by: Po-Ting Chen
---
.../drm/amd/display/dc/core/dc_hw_sequen
From: Jake Wang
[Why]
During DCC on/off, stutter period is calculated before DCC has fully
transitioned.
This results in incorrect stutter period calculation.
[How]
Trigger a full update when DCC changes between on/off.
Signed-off-by: Jake Wang
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DC v3.2.139
* FW v0.0.69
* Improvements across DP, eDP, DMUB, MPO, etc
--
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.68
Aric Cyr (4):
drm/amd/display: Change default policy for MPO with mul
capable panels when enabling/disabling
all
Signed-off-by: Mikita Lipski
Reviewed-by: Nicholas Kazlauskas
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 22 +++--
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 21
From: Jimmy Kizito
[Why & How]
Add support for transmitting training pattern sequences for links whose
encoders have been dynamically assigned.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 ++
.
[how]
Remove DSCCLK validation because it's implicitly validated under DISPCLK
Signed-off-by: Nikola Cornij
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../dc/dml/dcn30/display_mode_vba_30.c| 64 ++-
1 file changed, 21 insertions(+), 43 deletions(-)
retry if within 100ms there is no disconnection call
to HDCP module.
Signed-off-by: Wenjing Liu
Reviewed-by: Nicholas Kazlauskas
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
From: "JinZe.Xu"
[Why]
This disablement would be specific for Nav10 and shouldn’t be propagated to the
other programs.
[How]
Power gating is controlled by driver.
Signed-off-by: JinZe.Xu
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
.../drm/amd/display/dc/dcn302/dcn302_hws
From: Ilya Bakoulin
[Why]
This change was found to break some high-refresh modes. Reverting
to unblock mainline.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Sung Lee
Acked-by: Stylon Wang
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 78 +++
.../drm/amd/display/dc/dcn21
From: Meenakshikumar Somasundaram
[Why & How]
SET_CONFIG transactions with DMUB is not used and removed.
Signed-off-by: Meenakshikumar Somasundaram
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4
1 file changed, 4 deletions(-)
From: Jayendran Ramani
[How]
Add call to get the last used VTOTAL from DC
Signed-off-by: Jayendran Ramani
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 42 +++
drivers/gpu/drm/amd/display/dc/dc_stream.h| 4 ++
.../dc
releasing MST resources.
Signed-off-by: Vladimir Stempen
Reviewed-by: Wenjing Liu
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc
From: Mikita Lipski
[why]
Allow specifying which panel to take PSR Residency
measurements from.
[how]
Pass panel instance to DMUB through GPINT in the upper
8 bits of the parameter.
Signed-off-by: Mikita Lipski
Reviewed-by: Nicholas Kazlauskas
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd
From: Jimmy Kizito
[Why & How]
Add functionality useful for DP equalization phase of link training to
public interface.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 22 +--
.../gpu/drm/amd/dis
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index c0fbcbd4cbfc
-by: Stylon Wang
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 09bbec4dab7c..0b12299da93d 100644
--- a/drivers
: Krunoslav Kovac
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 2
From: Wesley Chalmers
[WHY]
HW has handed down a new sequence which requires access to the FIFO
ERRDET SW Override register.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 10 +++
.../gpu/drm/amd
From: Roy Chan
[Why]
Found a use case (IPKVM) that DP-VGA active dongle does
not return any EDID and the mentioned commit broke it.
[How]
This reverts "Disconnect non-DP with no EDID"
Signed-off-by: Roy Chan
Reviewed-by: Chris Park
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/
From: Fangzhi Zuo
[Why & How]
Add debugfs entry to force dsc decoding at PCON when DSC capable
external RX is connected. In such case, it is free to test DSC
decoding at external RX or at PCON.
Signed-off-by: Fangzhi Zuo
Reviewed-by: Hersen Wu
Acked-by: Stylon Wang
---
.../gpu/drm
From: Wesley Chalmers
[WHY]
HW has handed down a new sequence that requires access to these
registers.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 26 ++
.../gpu/drm/amd/display/dc/dcn20
From: Eric Bernstein
[Why]
There is an assert in cases where transition from ODM 2:1
to ODM 1:1 (bypass)
[How]
Remove assert since this case is now valid.
Update diags tests for ODM transitions.
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
drivers
From: Wesley Chalmers
[WHY]
For DCN30 and later, there is no data in DML arrays indexed by state at
index num_states.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 14 +++---
1 file
ion caused, which
has now been cleared.
[HOW]
In hdcp display removal, change CP to DESIRED if at the moment CP
is ENABLED before the auth reset and removal of linked list element.
Signed-off-by: Dingchen (David) Zhang
Signed-off-by: Qingqing Zhuo
Reviewed-by: Rodrigo Siqueira
Acked-by: S
ff-by: Aric Cyr
Reviewed-by: Krunoslav Kovac
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index cd864cc
From: Wesley Chalmers
[WHY]
DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when
changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dcn20
From: Wyatt Wood
Signed-off-by: Wyatt Wood
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index b4104b7422d8
[Why]
A new change that simplifies the ASSR enabling and guarding is found
that also fixes regression on some embedded panels.
[How]
Revert the ASSR changes in preparation for upcoming patch.
Signed-off-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 54
Previous ASSR-enabling patches cause blank screen on some embedded
panels. This patch set minimize the changes made to code logic prior to
the ASSR change and also improve on code readability.
Stylon Wang (2):
drm/amd/display: Revert "Re-enable 'Guard ASSR with internal display
fl
display flag
Signed-off-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cc62124b0b82
[Why]
A new change that simplifies the ASSR enabling and guarding is found
that also fixes regression on some embedded panels.
[How]
Revert the ASSR changes in preparation for upcoming patch.
Reviewed-by: Alex Deucher
Signed-off-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c
display flag
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=213779
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1620
Reviewed-by: Alex Deucher
Signed-off-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions
Previous ASSR-enabling patches cause blank screen on some embedded
panels. This patch set minimize the changes made to code logic prior to
the ASSR change and also improve on code readability.
Changes from prior rev1 to now:
v2:
- Update reviewed-by and bug links
Stylon Wang (2):
drm/amd
ASSR implementation was already in DC and DM guarded by
CONFIG_DRM_AMD_DC_HDCP. This patch enables ASSR if display
declares such support in DPCD.
Signed-off-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16
1 file changed, 16 insertions(+)
diff --git a
EDID parsing in S3 resume pushes new display modes
to probed_modes list but doesn't consolidate to actual
mode list. This creates a race condition when
amdgpu_dm_connector_ddc_get_modes() re-initializes the
list head without walking the list and results in memory leak.
Signed-off-by: Stylon
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix MST bugs
- Fix ODM combine debugfs
- Fix DML calculations
- Fix 2nd DPIA encoder issue
- Fix AUX-based backlight control
- Fix on MPO+ODM use case
- Fix DCCG clock programming
- Improvements on replay
- Improvements
From: Alvin Lee
[Description]
Before enabling the phantom OTG for an update we
must enable DPG to avoid underflow.
Reviewed-by: Samson Tam
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 50 +--
.../drm/amd/display/dc/dcn20
underflow due to phantom HUBP being blanked by default)
Reviewed-by: Samson Tam
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10
From: Aurabindo Pillai
[Why&How]
Set a default return value of -ENOTSUPP to indicate that the hardware
does not support querying ODM Combine mode.
Reviewed-by: Rodrigo Siqueira
Acked-by: Stylon Wang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgp
From: Bhawanpreet Lakha
Dirty rect can be used with replay, so enable them to allow for more
powersaving.
Reviewed-by: Sun peng Li
Acked-by: Stylon Wang
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1
[How]
Only check DCN registers if we aren't using AUX based brightness control.
Reviewed-by: Wenjing Liu
Acked-by: Stylon Wang
Signed-off-by: Swapnil Patel
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/
1 - 100 of 215 matches
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