pci_domain_nr<https://elixir.bootlin.com/linux/latest/C/ident/pci_domain_nr>(pdev->bus<https://elixir.bootlin.com/linux/latest/C/ident/bus>)
David
From: Roy Sun
Sent: Tuesday, April 20, 2021 8:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Sun, R
ot;Gu, JiaWei
(Will)"
Date: Thursday, April 22, 2021 at 8:25 PM
To: Christian König ,
"amd-gfx@lists.freedesktop.org"
Cc: "Deucher, Alexander" , "StDenis, Tom"
, "Nieto, David M"
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface
[AMD O
useful for the user to be
able to display in a simple way the VBIOS version in their system if they
happen to encounter an issue.
Regards,
David
From: Christian König
Date: Wednesday, April 28, 2021 at 12:15 AM
To: "Nieto, David M" , "Gu, JiaWei (Will)"
, "amd-gfx@li
list ; Sun,
Roy ; Nieto, David M
Subject: Re: [PATCH 1/2] drm/scheduler: Change scheduled fence track
I had to rebase them and was on sick leave last week.
Changed a few things on patch #1 and pushed the result a minute ago.
Christian.
Am 04.05.21 um 22:23 schrieb Alex Deucher:
> Did you p
From: Kees Cook
Sent: Saturday, May 8, 2021 2:51 AM
To: Gu, JiaWei (Will)
Cc: Deucher, Alexander ; StDenis, Tom
; Christian König ;
amd-gfx@lists.freedesktop.org ; Nieto, David M
; linux-n...@vger.kernel.org
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface
On Sat, May 08
hought,
> __u8 serial[16] in drm_amdgpu_info_vbios is a bit redundant, sysfs
> serial_number already exposes it.
>
> Is it fine to abandon it from drm_amdgpu_info_vbios struct? @Alex Deucher
> @Nieto, David M
>
> Best regards,
> Jiawei
>
> -Original Message-
, 2021 12:13:07 AM
To: Nieto, David M
Cc: Alex Deucher ; amd-gfx list
; Kees Cook ; Deng, Emily
Subject: RE: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios
[AMD Official Use Only - Internal Distribution Only]
Hi David,
What I meant is to ONLY delete the serial[16] from
me we can make a such
an assumption for sysfs nodes…
I think there is value in having both tbh.
Regards,
David
From: Christian König
Date: Monday, May 10, 2021 at 6:48 AM
To: "Nieto, David M" , "Gu, JiaWei (Will)"
Cc: Alex Deucher , "Deng, Emily" ,
Kees Co
From: Gu, JiaWei (Will)
Sent: Monday, May 10, 2021 7:23 PM
To: Nieto, David M ; Christian König
Cc: Alex Deucher ; Deng, Emily ;
Kees Cook ; amd-gfx list
Subject: RE: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios
[AMD Official Use Only - Internal Distribution Only
-gfx list ; Deng, Emily ;
Alex Deucher ; Nieto, David M
Subject: Re: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios
Yeah, but umr is making strong use of sysfs as well.
The only justification of this interface would be if we want to use it in Mesa.
And I agree with Marek that
[AMD Official Use Only - Internal Distribution Only]
The local variables need to be initialized to zero, since amdgpu_ctx_fence_time
accumulates and does not initialize
David
From: Christian König
Sent: Tuesday, May 11, 2021 12:53 AM
To: Nieto, David M ; amd
[AMD Official Use Only - Internal Distribution Only]
yep, you are right...
I'll make those changes.
David
From: Christian König
Sent: Tuesday, May 11, 2021 11:56 PM
To: Nieto, David M ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu
[AMD Official Use Only - Internal Distribution Only]
DOS line endings? That is weird
I corrected the issues that showed in checkpatch.pl (the > 80 lines)
I'll re-upload
From: Christian König
Sent: Thursday, May 13, 2021 1:11 AM
To: Nieto, David M ;
nk ; Ming, Davis
; Liu, Shaoyun ; Zhou, Peng Ju
; Chen, JingWen ; Chen, Horace
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH 4/5] drm/amdgpu: Initialize Aldebaran RLC function pointers
In SRIOV, RLC function pointers must be initialized early as
we rely on the RLCG interface for all GC regis
u
; Chen, JingWen ; Chen, Horace
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH 5/5] drm/amdgpu: Modify indirect register access for gfx9 sriov
Expand RLCG interface for new GC read & write commands.
New interface will only be used if the PF enables the flag in pf2vf msg.
Signed-off-
Sent: Wednesday, December 15, 2021 10:55 AM
To: amd-gfx@lists.freedesktop.org ; Deng, Emily
; Liu, Monk ; Ming, Davis
; Liu, Shaoyun ; Zhou, Peng Ju
; Chen, JingWen ; Chen, Horace
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH 2/5] drm/amdgpu: Modify indirect register access for gmc_v9_
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH 1/5] drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitions
Add helper macros to change register access
from direct to indirect.
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 5 +
1 file changed, 5
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH 3/5] drm/amdgpu: Modify indirect register access for
amdkfd_gfx_v9 sriov
Modify GC register access from MMIO to RLCG if the indirect
flag is set
Signed-off-by: Victor Skvortsov
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 27
would be good to document it.
From: Skvortsov, Victor
Sent: Wednesday, December 15, 2021 11:18 AM
To: Nieto, David M ; amd-gfx@lists.freedesktop.org
; Deng, Emily ; Liu, Monk
; Ming, Davis ; Liu, Shaoyun
; Zhou, Peng Ju ; Chen, JingWen
; Chen, Horace
Subject
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH v3 1/5] drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitions
Add helper macros to change register access
from direct to indirect.
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 5 +
1 file changed, 5
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH v3 2/5] drm/amdgpu: Modify indirect register access for
gmc_v9_0 sriov
Modify GC register access from MMIO to RLCG if the
indirect flag is set
v2: Replaced ternary operator with if-else for better
readability
Signed-off-by: Victor Skvortsov
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH v3 3/5] drm/amdgpu: Modify indirect register access for
amdkfd_gfx_v9 sriov
Modify GC register access from MMIO to RLCG if the indirect
flag is set
Signed-off-by: Victor Skvortsov
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 27
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH v3 4/5] drm/amdgpu: get xgmi info before ip_init
Driver needs to call get_xgmi_info() before ip_init
to determine whether it needs to handle a pending hive reset.
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7
; Nieto, David M
Cc: Skvortsov, Victor
Subject: [PATCH v3 5/5] drm/amdgpu: Modify indirect register access for gfx9
sriov
Expand RLCG interface for new GC read & write commands.
New interface will only be used if the PF enables the flag in pf2vf msg.
v2: Added a description for the scratch regis
[AMD Public Use]
I dont think the pp_nodes expose the vclk dclk nodes, but it might be better to
rework this patch to expose those instead, and just add the voltages...
From: Lazar, Lijo
Sent: Sunday, May 16, 2021 11:28 PM
To: Nieto, David M ; amd-gfx
To: Gu, JiaWei (Will) ; amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Nieto, David M
Subject: Re: [PATCH] drm/amdgpu: Expose rfc4122 compliant UUID
Am 17.05.21 um 07:54 schrieb Jiawei Gu:
> Introduce an RFC 4122 compliant UUID for the GPUs derived
> from the unique GPU serial number
Sent: Monday, May 17, 2021 7:11 PM
To: Koenig, Christian ; amd-gfx@lists.freedesktop.org
; Nieto, David M ;
mar...@gmail.com ; Deucher, Alexander
Cc: Deng, Emily
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface
[AMD Official Use Only - Internal Distribution Only]
So I guess the db
[Public]
Yes, let's remove that too,
Thanks,
David
From: Gu, JiaWei (Will)
Sent: Monday, May 17, 2021 8:07 PM
To: Nieto, David M ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
; mar...@gmail.com ; Deucher,
Alexander
Cc: Deng, Emily
Subject: RE: [
[Public]
That looks like the right output to me.
From: Gu, JiaWei (Will)
Sent: Monday, May 17, 2021 10:58 PM
To: Nieto, David M ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
; mar...@gmail.com ; Deucher,
Alexander
Cc: Deng, Emily
Subject: RE: [PATCH
)
Cc: amd-gfx list ; Deng, Emily
; Nieto, David M
Subject: Re: [PATCH] drm/amdgpu: Expose rfc4122 compliant UUID
On Mon, May 17, 2021 at 1:54 AM Jiawei Gu wrote:
>
> Introduce an RFC 4122 compliant UUID for the GPUs derived
> from the unique GPU serial number (from Vega10) on gpus.
>
[Public]
That is correct, it is 0x11030008, that matches the FW information.
From: Lazar, Lijo
Sent: Tuesday, May 18, 2021 3:50 AM
To: Gu, JiaWei (Will) ; Nieto, David M
; Koenig, Christian ;
amd-gfx@lists.freedesktop.org ; mar...@gmail.com
; Deucher
: Wednesday, May 19, 2021 3:58:35 AM
To: Nieto, David M ; Alex Deucher ;
Gu, JiaWei (Will)
Cc: Deng, Emily ; amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: Expose rfc4122 compliant UUID
Well I don't think generating an UUID in the kernel makes sense in general.
What we can do is to expos
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