Re: [PATCH 2/2] drm/amdgpu: cleanup PTE flag generation

Maybe  it's not necessary to separate the mtype from the get_vm_pte function , so we just need one  asic specific functions (get_vm_pte) . What make me confusing originally is  the  the  logic  to setup the  PTE flag.   We first map the  UAPI flags to HW specific PTE flag , save it into mapping

Re: [PATCH] drm/amdkfd: Swap trap temporary registers in gfx10 trap handler

Reviewed by: shaoyun liu On 2019-09-12 3:13 p.m., Cornwall, Jay wrote: > ttmp[4:5] hold information useful to the debugger. Use ttmp[14:15] > instead, aligning implementation with gfx9 trap handler. > > Signed-off-by: Jay Cornwall > --- > drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h

Re: [PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path

Probably rename to sdma_rlc to avoid the  confusion of  rlc used in other amdgpu driver . Regards shaoyun.liu On 2019-09-22 11:56 p.m., Zhao, Yong wrote: > The old name is prone to confusion. The register offset is for a RLC queue > rather than a SDMA engine. The value is not a base address, bu

[PATCH] drm/amdgpu: Add NAVI12 support from kfd side

Add device info for both navi12 PF and VF Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4 Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/a

[PATCH] drm/amdkfd: Add NAVI12 support from kfd side

Add device info for both navi12 PF and VF Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4 Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/a

Re: [PATCH] drm/amdkfd: Add NAVI12 support from kfd side

From: amd-gfx <mailto:amd-gfx-boun...@lists.freedesktop.org> on behalf of Liu, Shaoyun <mailto:shaoyun@amd.com> Sent: Tuesday, September 24, 2019 6:16 PM To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> <mailto:amd-gfx@lists.freedesktop.org> Cc: Li

[PATCH] drm/amdkfd: Add NAVI12 support from kfd side

Add device info for both navi12 PF and VF Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4 Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/a

RE: [PATCH] drm/amdgpu: Add NAVI12 support from kfd side

I sent out another change that set the asic_family as CHIP_NAVI10 since from KFD side there is no difference for navi10 and navi12. Regards Shaoyun.liu -Original Message- From: Kuehling, Felix Sent: Wednesday, September 25, 2019 11:23 AM To: Liu, Shaoyun ; amd-gfx

[PATCH] drm/amdkfd: use navi12 specific family id for navi12 code path

Keep the same use of CHIP_IDs for navi12 in kfd Change-Id: I5e52bbc058be51e79553147732a571a604537b7c Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_

Re: [PATCH] drm/amdkfd: use navi12 specific family id for navi12 code path

Ping. From: Liu, Shaoyun Sent: September 25, 2019 5:14:08 PM To: amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: [PATCH] drm/amdkfd: use navi12 specific family id for navi12 code path Keep the same use of CHIP_IDs for navi12 in kfd Change-Id

Re: [PATCH 2/2] drm/amdkfd: Query vmid pasid mapping through stored info

I think this is only for none-hws case .  HWS may  dynamic change the mapping and driver will not get updated .  If that's the case , please specify this is for none hardware scheduler case in the header . Regards shaoyun.liu On 2019-09-26 4:07 p.m., Kuehling, Felix wrote: > On 2019-09-26 3:46

[PATCH] drm/amdgpu : enable msix for amdgpu driver

We might used out of the msi resources in some cloud project which have a lot gpu devices(including PF and VF), msix can provide enough resources from system level view Change-Id: I9f03762074ac416c07f27b8f00c052ca93c7d6cb Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 ++

Re: [PATCH 2/2] drm/amdgpu: disable MSI-X on APUs

Thanks Alex and  Tom to catch and  revolve the issue .  I didn't do enough test on original test. We don't need to enable msix  on APU .   The serials is reviewed by shaoyun.liu Regards shaoyun.liu On 2019-10-03 10:13 a.m., Alex Deucher wrote: > Raven claims to support them, but seems to

Re: [PATCH] drm/amdgpu: improve MSI-X handling (v3)

Looks good to me . Reviewed-by: Shaoyun liu On 2019-10-03 1:33 p.m., Tom St Denis wrote: Tested-by: Tom St Denis Cheers, Tom On Thu, Oct 3, 2019 at 1:30 PM Alex Deucher wrote: Check the number of sup

[PATCH] drm/amdkfd: remove unnecessary warning message on gpu reset

In XGMI configuration, more than one asic can be reset at same time, kfd is able to handle this and no need to trigger the warning Change-Id: If339503860e86ee1dbeed294ba1c103fcce70b7b Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 - 1 file changed, 1 deletion(-) diff -

Re: [PATCH] drm/amdkfd: fix potential null pointer dereference on pointer peer_dev

From the comments , "we will  loop GPUs that already be processed (with lower value of proximity_domain) ",  the device should already been added into the  topology_device_list.  So in this case , kfd_topology_device_by_proximity_domain will not return a NULL pointer.  If you really get the nu

Re: [PATCH 1/1] drm/amdkfd: Consistently apply noretry setting

Reviewed-by : Shaoyun.liu < shaoyun@amd.com> I manually applied the change and  verified on vega10 on visualization  which we do have  retry vm fault issue . With  this patch , the no-retry interrupt delivered as expected and I don't see  the interrupt storm. Regards shaoyun.liu On 2019-

[PATCH] drm/amdkfd: Add DID for Navi12

Add device id for KFD Change-Id: I44e8e884d0dc86209de7c0b6f4784d06ee371079 Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 2514263..

Re: [PATCH] drm/amdkfd/kfd_mqd_manager_v10: Fix missing break in switch statement

This one properly in purpose , The mqd init for CP and  COMPUTE will have the same  routine . Regard sshaoyun.liu On 2019-07-21 6:59 p.m., Gustavo A. R. Silva wrote: > Add missing break statement in order to prevent the code from falling > through to case KFD_MQD_TYPE_COMPUTE. > > This bug was

Re: [PATCH] drm/amdkfd/kfd_mqd_manager_v10: Fix missing break in switch statement

PE_CP: > > case KFD_MQD_TYPE_CP: > case KFD_MQD_TYPE_COMPUTE: > pr_debug("%s@%i\n", __func__, __LINE__); > mqd->allocate_mqd = allocate_mqd; > > Thanks > -- > Gustavo > > >> Alex >> _

Re: [PATCH] drm/amdkfd/kfd_mqd_manager_v10: Avoid fall-through warning

Reviewed-by:  shaoyunl On 2019-07-22 1:47 p.m., Gustavo A. R. Silva wrote: > In preparation to enabling -Wimplicit-fallthrough, this patch silences > the following warning: > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.c: In function > ‘mqd_manager_init_v10’: > ./include/linux/dyn

Re: [PATCH 3/3] drm/amdkfd: Save/restore vcc on gfx10

Series is: reviewed-by: shaoyunl On 2019-07-29 11:31 a.m., Cornwall, Jay wrote: > VCC moved out of user SGPR allocation in gfx10. It's now stored > in SGPRs 106-107. > > Also fixes incorrect SGPR read offsets. > > Cc: Shaoyun Liu > Signed-off-by: Jay Cornwall > --- > drivers/gpu/drm/amd/amdkf

RE: [PATCH 13/23] drm/amdgpu/mxgpu: add support for mailbox communication

gfx list; dl.SRDC_SW_GPUVirtualization; Liu, Shaoyun Subject: RE: [PATCH 13/23] drm/amdgpu/mxgpu: add support for mailbox communication > -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Tuesday, December 20, 2016 7:25 AM > To: Yu, Xiangliang

Move kiq ring lock out of virt strucure

Please have a look. Regards Shaoyun.liu 0001-drm-amdgpu-Move-kiq-ring-lock-out-of-virt-structure.patch Description: 0001-drm-amdgpu-Move-kiq-ring-lock-out-of-virt-structure.patch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.fre

Set invalidation reg set used in amdgpu to avoid the confliction for vega10

Please have a look. Regards Shaoyun.liu 0001-drm-amdgpu-Reserve-0-2-invalidation-reg-sets-for-non.patch Description: 0001-drm-amdgpu-Reserve-0-2-invalidation-reg-sets-for-non.patch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.f

RE: Move kiq ring lock out of virt strucure

Thanks , Andres . Changed as suggested . Regards Shaoyun.liu -Original Message- From: Andres Rodriguez [mailto:andre...@gmail.com] Sent: Friday, April 28, 2017 5:41 PM To: Liu, Shaoyun; amd-gfx list (amd-gfx@lists.freedesktop.org); Deucher, Alexander Cc: brahma_sw_dev Subject: Re

RE: [PATCH] drm/amdgpu: Reserve 0-2 invalidation reg sets for none-amdgpu usages

Thanks Alex. -Original Message- From: Deucher, Alexander Sent: Monday, May 01, 2017 4:47 PM To: Liu, Shaoyun Cc: Kuehling, Felix Subject: RE: [PATCH] drm/amdgpu: Reserve 0-2 invalidation reg sets for none-amdgpu usages Christian sent his RB this morning I think? Or was that

RE: [PATCH 0/5] GFX9 KIQ

I don't have any test for KCQ , but KFD use the KIQ to invalidate_tlbs , I try to add some print message in the code to prove it go through the new code path , but seems I don't see any messages I added. I tried pr_info , pr_err and printk , DRM_ERROR and nothing works , anything changed

RE: [PATCH 0/5] GFX9 KIQ

: Deucher, Alexander Sent: Wednesday, May 24, 2017 7:14 AM To: Liu, Shaoyun; Alex Deucher; StDenis, Tom Cc: amd-gfx list Subject: RE: [PATCH 0/5] GFX9 KIQ > -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Liu, Shaoyun > Sent: Tue

RE: [PATCH umr] Add --vm-write/--vm-read to replace the --vram-* commands to be less confusing

Reviewed-By : Shaoyun.liu -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Tom St Denis Sent: Wednesday, September 13, 2017 2:27 PM To: amd-gfx@lists.freedesktop.org Cc: StDenis, Tom Subject: [PATCH umr] Add --vm-write/--vm-read to replace the

RE: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic

: Christian König [mailto:deathsim...@vodafone.de] Sent: Friday, June 30, 2017 3:57 AM To: Michel Dänzer; Liu, Shaoyun Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic Am 30.06.2017 um 03:21 schrieb Michel Dänzer: > On 30/06/17 06:08

RE: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic

u From: Liu, Monk Sent: Monday, July 03, 2017 5:45 AM To: Liu, Shaoyun; Christian König; Michel Dänzer Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic Hi Shaoyun looks you want to make KIQ reg access be atomic & UN-interrupt

RE: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic

It's inside the gmc_v9_0_gart_flush_gpu_tlb function where it calls the nbio_v6_0_hdp_flush . I already sent out the commit for review .you can check for details . Regards Shaoyun.liu From: Liu, Monk Sent: Tuesday, July 04, 2017 11:26 PM To: Liu, Shaoyun; Christian König; Michel Dänz

RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine

Thanks . Split the change as suggested and pushed . Regards Shaoyun.liu -Original Message- From: Deucher, Alexander Sent: Wednesday, July 05, 2017 9:17 AM To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush

RE: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine

Let me try again. Shaoyun.liu -Original Message- From: Alex Deucher [mailto:alexdeuc...@gmail.com] Sent: Wednesday, July 05, 2017 1:15 PM To: Liu, Shaoyun Cc: Deucher, Alexander; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine On

RE: [PATCH] drm/amdgpu: Fix KFD oversubscription by tracking queues correctly

There is a function get_mec_num use the field , but seems no one call it , maybe remove it as well. Regards Shaoyun.liu -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Andres Rodriguez Sent: Thursday, July 13, 2017 3:54 PM To: Kuehling,

RE: [PATCH 3/3] drm/amdgpu: Clear active for HIQ in RLC_CP_SCHEDULERS

I'd like to avoid add KFD related stuff into the adev structure and keep the similar interface as hdp_load. If nobody mind of one patch that across different code directories I can squash them into one patch. Regards Shaoyun.liu -Original Message- From: amd-gfx [mailto:amd-gfx-

RE: [PATCH] drm/amdgpu: Set the bit of ip_block_mask correspond to the IP block define

how to set the bit mask after check the ip type defines and they are fixed for amdgpu driver . Regards Shaoyun.liu -Original Message- From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] Sent: Thursday, February 01, 2018 3:17 PM To: Liu, Shaoyun; amd-gfx

RE: [PATCH] drm/amdgpu: Set the bit of ip_block_mask correspond to the IP block define

, Shaoyun Cc: Koenig, Christian; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: Set the bit of ip_block_mask correspond to the IP block define On Thu, Feb 1, 2018 at 3:32 PM, Liu, Shaoyun wrote: > Can you provide the example of which different block with the same type and > why w

RE: [PATCH 1/2] drm/amdgpu: Set module parameter for emulation

using those on both emulator and real silicon. Thanks, John >-Original Message- >From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf >Of Alex Deucher >Sent: Thursday, February 01, 2018 3:31 PM >To: Koenig, Christian >Cc: amd-gfx list; Liu, Shaoyun >Su

RE: [PATCH] drm/amdgpu: Set the bit of ip_block_mask correspond to the IP block define

:51 PM To: Liu, Shaoyun Cc: Koenig, Christian; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: Set the bit of ip_block_mask correspond to the IP block define On Thu, Feb 1, 2018 at 3:44 PM, Liu, Shaoyun wrote: > In that case , even existing implementation need to be changed and

RE: [PATCH] drm/amdgpu: Set the bit of ip_block_mask correspond to the IP block define

Do you mind to change the DRM_DEBUG to DRM_INFO for this message ? -Original Message- From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] Sent: Thursday, February 01, 2018 4:11 PM To: Liu, Shaoyun; Alex Deucher; Bridgman, John Cc: Koenig, Christian; amd-gfx

RE: [PATCH] drm/amdgpu: Basic emulation support

-Original Message- From: Alex Deucher [mailto:alexdeuc...@gmail.com] Sent: Monday, February 05, 2018 12:53 PM To: Bridgman, John Cc: Koenig, Christian; Liu, Shaoyun; amd-gfx list Subject: Re: [PATCH] drm/amdgpu: Basic emulation support On Mon, Feb 5, 2018 at 12:34 PM, Bridgman, John

RE: [PATCH] drm/amdgpu: Add place holder for soc15 asic init on emulation

ginal Message- From: Alex Deucher [mailto:alexdeuc...@gmail.com] Sent: Tuesday, February 06, 2018 4:46 PM To: Liu, Shaoyun Cc: amd-gfx list Subject: Re: [PATCH] drm/amdgpu: Add place holder for soc15 asic init on emulation On Tue, Feb 6, 2018 at 4:41 PM, Shaoyun Liu wrote: > C

RE: [PATCH] drm/amdgpu: Add place holder for soc15 asic init on emulation

[mailto:alexdeuc...@gmail.com] Sent: Tuesday, February 06, 2018 5:03 PM To: Liu, Shaoyun Cc: Bridgman, John; amd-gfx list Subject: Re: [PATCH] drm/amdgpu: Add place holder for soc15 asic init on emulation On Tue, Feb 6, 2018 at 4:55 PM, Liu, Shaoyun wrote: > Ye, I try to put the asic speci

RE: [PATCH] drm/amdgpu: Add place holder for soc15 asic init on emulation

Thanks . Can I add Review-By you for this patch ? Shaoyun.liu -Original Message- From: Deucher, Alexander Sent: Tuesday, February 06, 2018 5:37 PM To: Liu, Shaoyun; Alex Deucher Cc: amd-gfx list; Bridgman, John Subject: RE: [PATCH] drm/amdgpu: Add place holder for soc15 asic init on

RE: [PATCH 3/4] drm/amdkfd: Add CWSR support

e big ( around 22M for vega10) , so we don't want to allocate them in kernel . Other comments in line . Regards Shaoyun.liu -Original Message- From: Oded Gabbay [mailto:oded.gab...@gmail.com] Sent: Sunday, November 19, 2017 8:38 AM To: Kuehling, Felix Cc: amd-gfx list; Liu, Shaoyun;

RE: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file

] Sent: Monday, November 27, 2017 2:17 PM To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file First of let us fix the obvious style problems. Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: > Change-Id: I654d02891b80f3457ddcd80d6a8e

RE: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file

Hi , This file is copied from HW asic bring up team . The defines here are the same as what we already have under amd/include/asic_reg/vega10/soc15ip.h . Compare to VEGA10, the same IP could have different base offset defines , so the original soc15ip.h will not works for other asic . I

RE: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file

, > Christian. > >> >> Regards, >>Felix >> >>> Please start by fixing at least the obvious style problems before >>> resending. >>> >>> Thanks, >>> Christian. >>> >>> Am 27.11.2017 20:29 schrieb "

RE: [PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

t it in another change so this patch will looks much more cleaner . Regards Shaoyun.liu -Original Message- From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] Sent: Wednesday, November 29, 2017 3:05 PM To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 2/5]

RE: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

replace the SOC15_REG_OFFSET used in amdgpu_gds_reg_offset[] Regards Shaoyun.liu -Original Message- From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] Sent: Wednesday, November 29, 2017 3:08 PM To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 3/5] drm/amdgpu

RE: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

[mailto:ckoenig.leichtzumer...@gmail.com] Sent: Thursday, November 30, 2017 3:42 AM To: Liu, Shaoyun; Koenig, Christian; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array I would rather go with something like this: #define SOC15_REG_GOLDEN_VALUE(ip

RE: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

, mmUVD_NO_OP), 0), ... Can we avoid use fixed IP_BASE_INST*_SEG* + mmReg for them ? Regards Shaoyun.liu -Original Message- From: Koenig, Christian Sent: Thursday, November 30, 2017 3:00 PM To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 3/5] drm/amdgpu: Avoid to use

RE: [PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

Please ignore this change , forgot to include uvd related changes as suggested . Regards Shaoayun.liu -Original Message- From: Liu, Shaoyun Sent: Friday, December 01, 2017 2:58 PM To: amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: [PATCH 3/5] drm/amdgpu: Avoid use

RE: [PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

Hi , Christian Do you have time to continue review them ? Regards Shaoyun.liu -Original Message- From: Liu, Shaoyun Sent: Friday, December 01, 2017 3:13 PM To: amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: [PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const

RE: [PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

Thanks a lot . Regards Shaoyun.liu -Original Message- From: Koenig, Christian Sent: Thursday, December 07, 2017 12:13 PM To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array Hi Shaoyun, I didn't

RE: PCIe3 atomics requirement for amdkfd

I think currently atomic Ops are only used in AQL package which is only available for ROCm , graphics workload will not use AQL package. Regards Shaoyun.liu -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Tom Stellard Sent: Wednesday, Janua

RE: [PATCH 3/3] drm/amdgpu: reset kfd during amdgpu reset

mpute stuff running and actually not hang . Regards Shaoyun.liu -Original Message- From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] Sent: Friday, January 26, 2018 12:41 PM To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 3/3] drm/amdgpu: reset kfd d

RE: [PATCH 3/3] drm/amdgpu: reset kfd during amdgpu reset

Sorry , I meant if I use the "false" flag and gpu_recovery is not enabled , the reset will be ignored. -Original Message----- From: Liu, Shaoyun Sent: Friday, January 26, 2018 12:54 PM To: Koenig, Christian; amd-gfx@lists.freedesktop.org Subject: RE: [PATCH 3/3] drm/amdgpu:

RE: [PATCH 3/3] drm/amdgpu: reset kfd during amdgpu reset

Ok, the wrong hang detection when amdgpu_gpu_recovery is enabled may be another issue , we can fix it later . Changed to 'false' flag as suggested and submitted . Regards Shaoyun.liu -Original Message- From: Koenig, Christian Sent: Friday, January 26, 2018 1:28 PM To: Li

RE: [PATCH 3/3] drm/amdgpu: reset kfd during amdgpu reset

... And then use the user configurable option as bitmask to enable/disable GPU recovery for each trigger source. Regards, Christian. Am 26.01.2018 um 19:37 schrieb Liu, Shaoyun: > Ok, the wrong hang detection when amdgpu_gpu_recovery is enabled may be > another issue , we can fix it

RE: [PATCH 3/3] drm/amdgpu: reset kfd during amdgpu reset

Yes, understood . I already rebased the changes on amd-kfd-staging and add you and Christian as reviewer. Regards Shaoyun.liu -Original Message- From: Kuehling, Felix Sent: Friday, January 26, 2018 2:47 PM To: Liu, Shaoyun; Koenig, Christian; amd-gfx@lists.freedesktop.org Subject

RE: [PATCH] drm/amdkfd: add/remove kfd queues through on stop/start KFD scheduling

[AMD Official Use Only - AMD Internal Distribution Only] Ping -Original Message- From: Liu, Shaoyun Sent: Friday, October 4, 2024 12:08 PM To: amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: [PATCH] drm/amdkfd: add/remove kfd queues through on stop/start KFD scheduling Add

RE: [PATCH] drm/amdgpu: Increase MES log buffer to dump mes scratch data

[AMD Official Use Only - AMD Internal Distribution Only] Ping . -Original Message- From: Liu, Shaoyun Sent: Thursday, October 10, 2024 12:10 PM To: amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: [PATCH] drm/amdgpu: Increase MES log buffer to dump mes scratch data MES internal

RE: [PATCH] drm/amd/amdkfd: add/remove kfd queues on start/stop KFD scheduling

[AMD Official Use Only - AMD Internal Distribution Only] Good catch . Thanks . I will sent out another review for that . Regards Shaoyun.liu From: Yang, Philip Sent: Thursday, October 17, 2024 3:47 PM To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/amdkfd: add

RE: [PATCH] drm/amdgpu: Increase MES log buffer to dump mes scratch data

[AMD Official Use Only - AMD Internal Distribution Only] ping -Original Message- From: amd-gfx On Behalf Of Liu, Shaoyun Sent: Friday, October 11, 2024 12:57 PM To: amd-gfx@lists.freedesktop.org Subject: RE: [PATCH] drm/amdgpu: Increase MES log buffer to dump mes scratch data [AMD

RE: [PATCH] drm/amd/amdgpu: limit single process inside MES

Sent: Thursday, October 24, 2024 9:21 AM To: Liu, Shaoyun Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amd/amdgpu: limit single process inside MES On Wed, Oct 23, 2024 at 8:48 PM Shaoyun Liu wrote: > > This is for MES to limit only one process for the user queues > >

RE: [PATCH] drm/amd/include : Update MES v12 API for fence update

[AMD Official Use Only - AMD Internal Distribution Only] ping -Original Message- From: Liu, Shaoyun Sent: Wednesday, February 5, 2025 1:41 PM To: amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: [PATCH] drm/amd/include : Update MES v12 API for fence update MES fence_value will

RE: [PATCH v3] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11

, lin ; Chen, JingWen (Wayne) ; Liu, Shaoyun Subject: [PATCH v3] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11 This commit introduces enhancements to the handling of the cleaner shader fence in the AMDGPU MES driver: - The MES (Microcode Execution Scheduler) now

RE: [PATCH V3 2/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11

Chen, JingWen (Wayne) ; Liu, Shaoyun Subject: Re: [PATCH V3 2/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11 Am 07.02.25 um 15:43 schrieb Alex Deucher: > From: Srinivasan Shanmugam > > This commit introduces enhancements to the handling of the cleaner >

RE: [PATCH V4 2/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11

n.liu -Original Message- From: Deucher, Alexander Sent: Monday, February 10, 2025 11:28 AM To: amd-gfx@lists.freedesktop.org Cc: SHANMUGAM, SRINIVASAN ; cao, lin ; Chen, JingWen (Wayne) ; Koenig, Christian ; Deucher, Alexander ; Liu, Shaoyun Subject: [PATCH V4 2/2] drm/amdgpu/mes: Add cl

RE: [PATCH 2/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX12

To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian ; SHANMUGAM, SRINIVASAN ; Liu, Shaoyun Subject: [PATCH 2/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX12 This commit introduces enhancements to the handling of the cleaner shader fence

RE: [PATCH 2/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX12

n.liu -Original Message- From: Alex Deucher Sent: Tuesday, February 11, 2025 10:24 AM To: Liu, Shaoyun Cc: Deucher, Alexander ; amd-gfx@lists.freedesktop.org; Koenig, Christian ; SHANMUGAM, SRINIVASAN Subject: Re: [PATCH 2/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for

RE: [PATCH V5 1/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11

, JingWen (Wayne) ; Koenig, Christian ; Deucher, Alexander ; Liu, Shaoyun Subject: [PATCH V5 1/2] drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX11 From: Srinivasan Shanmugam This commit introduces enhancements to the handling of the cleaner shader fence in the AMDGPU MES

RE: [PATCH] drm/amd : Update MES API header file for v11 & v12

[AMD Official Use Only - AMD Internal Distribution Only] Sorry, please ignore this one . sent wrong patch. Regards Shaoyun.liu -Original Message- From: Liu, Shaoyun Sent: Friday, January 31, 2025 10:35 PM To: amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: [PATCH] drm/amd

RE: [RFC v1 0/2] Enable resume with different AMD SRIOV vGPUs

[AMD Official Use Only - AMD Internal Distribution Only] I think to resume with different SRIOV vGPUs depends on the hypervisor has the live migration support . Different Hypervisor have different implementation , basically it will call into the host gpu driver in different stage and host s

RE: [RFC v1 0/2] Enable resume with different AMD SRIOV vGPUs

January 14, 2025 8:48 PM To: Liu, Shaoyun Cc: Koenig, Christian ; Deucher, Alexander ; Pan, Xinhui ; airl...@gmail.com; sim...@ffwll.ch; Khatri, Sunil ; Lazar, Lijo ; Zhang, Hawking ; Limonciello, Mario ; Chen, Xiaogang ; Russell, Kent ; shuox@linux.alibaba.com; amd-gfx@lists.freedesktop.o

Re: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once

the pipe1 will not use mes, so no mes api is required for pipe1, but for pipe0, it's still the same requirement. Regards Shaoyun.liu Get Outlook for iOS<https://aka.ms/o0ukef> ________ From: Liu, Shaoyun Sent: Friday, February 14, 2025 12:46:27 PM To: Deucher,

RE: [PATCH 2/3] drm/amdgpu/mes: clean up SDMA HQD loop

[AMD Official Use Only - AMD Internal Distribution Only] Should the SDMA mask be ASIC specific ? I think some ASIC might need to be set to 0x3fc . Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Thursday, March 20, 2025 10:23 AM To: amd-gfx@lists.freedeskt

RE: [PATCH 1/2] drm/amdgpu/mes: optimize compute loop handling

[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Wednesday, March 19, 2025 12:24 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 1/2] drm/amdgpu/mes: optimize c

RE: [PATCH 3/3] drm/amdgpu/mes: warn on unexpected pipe numbers

[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Thursday, March 20, 2025 10:23 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 3/3] drm/amdgpu/mes: warn on une

RE: [PATCH 2/2] drm/amdgpu/mes12: optimize MES pipe FW version fetching

[AMD Official Use Only - AMD Internal Distribution Only] Looks good to me . Reviewed by : Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Monday, April 7, 2025 10:17 AM To: Deucher, Alexander Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 2/2] drm/a

RE: [PATCH 1/2] Documentation: update KIQ documentation

[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by : shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Monday, April 7, 2025 10:18 AM To: Deucher, Alexander Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 1/2] Documentation: update KIQ

RE: [PATCH] drm/amdgpu: Fix API status offset for MES queue reset

[AMD Official Use Only - AMD Internal Distribution Only] Looks good to me . Reviewed-By: Shaoyun.liu < shaoyun@amd.com> -Original Message- From: amd-gfx On Behalf Of Jesse.Zhang Sent: Sunday, April 27, 2025 10:40 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig,

RE: [PATCH] drm/amdgpu/userq: move runpm handling into core userq code

[AMD Official Use Only - AMD Internal Distribution Only] Looks good to me . Reviewed-by: Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Sunday, April 13, 2025 2:24 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amdgpu/user

RE: [PATCH 5/8] drm/amdgpu/mes12: add support for setting gang submit

: Tuesday, April 29, 2025 3:05 PM To: Liu, Shaoyun Cc: Chen, Michael ; Deucher, Alexander ; amd-gfx@lists.freedesktop.org; Khatri, Sunil ; Liang, Prike Subject: Re: [PATCH 5/8] drm/amdgpu/mes12: add support for setting gang submit On Tue, Apr 29, 2025 at 2:56 PM Liu, Shaoyun wrote: > >

RE: [PATCH 5/8] drm/amdgpu/mes12: add support for setting gang submit

[AMD Official Use Only - AMD Internal Distribution Only] Ye , that’s guide line , I believe that’s align with our legacy kiq usage . Shaoyun.liu From: Chen, Michael Sent: Tuesday, April 29, 2025 3:20 PM To: Alex Deucher ; Liu, Shaoyun Cc: Deucher, Alexander ; amd-gfx@lists.freedesktop.org

RE: [PATCH 5/8] drm/amdgpu/mes12: add support for setting gang submit

[AMD Official Use Only - AMD Internal Distribution Only] Correctly , the gang submission related stuff only used for scheduler pipe , kiq is for used for kernel driver only and should not expose to the user queue. Regards Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Ale

RE: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once

[AMD Official Use Only - AMD Internal Distribution Only] Ok . From MES point of view , we expecting both set_hw_resource and set_hw_resource_1 been called all the time. Reviewed-by: Shaoyun.liu From: Deucher, Alexander Sent: Friday, February 14, 2025 11:53 AM To: Liu, Shaoyun ; amd-gfx

RE: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once

change for this serials is good enough. Regards Shaoyun.liu From: Deucher, Alexander Sent: Friday, February 14, 2025 12:42 PM To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once [AMD Official Use Only - AMD Internal Distrib

RE: [PATCH 1/2] drm/amdgpu/mes11: allocate hw_resource_1 buffer once

[AMD Official Use Only - AMD Internal Distribution Only] Looks good to me . Reviewed-by: Shaoyun.liu < shaouyun@amd.com> -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Friday, February 14, 2025 10:19 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subje

RE: [PATCH 2/2] drm/amdgpu/mes12: allocate hw_resource_1 buffer once

[AMD Official Use Only - AMD Internal Distribution Only] I'd suggest remove the enable_uni_mes check, set_hw_resource_1 is always required for gfx12 and up. Especially after add the cleaner_shader_fence_addr there. Regards Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of A

RE: [PATCH 2/2] drm/amdgpu/mes11: drop amdgpu_mes_suspend()/amdgpu_mes_resume() calls

[AMD Official Use Only - AMD Internal Distribution Only] This series looks good to me . Reviewed-by :Shaoyun.liu -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Tuesday, February 25, 2025 10:10 AM To: Deucher, Alexander Cc: amd-gfx@lists.freedesktop.org Subject: Re: [

RE: [PATCH] drm/amdgpu/mes12: rework pipe selection for legacy queues

rsday, May 8, 2025 2:32 PM To: Deucher, Alexander ; amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: Re: [PATCH] drm/amdgpu/mes12: rework pipe selection for legacy queues [Public] From: Deucher, Alexander mailto:alexander.deuc...@amd.com>> Sent:

Re: [PATCH] drm/amdgpu/mes: add compatibility checks for set_hw_resource_1

op.org ; Liu, Shaoyun 主题: Re: [PATCH] drm/amdgpu/mes: add compatibility checks for set_hw_resource_1 Ping? On Tue, Jun 17, 2025 at 12:47 PM Alex Deucher wrote: > > Seems some older MES firmware versions do not properly support > this packet. Add back some the compatibility checks. &g

RE: [PATCH] drm/amdgpu/mes: add compatibility checks for set_hw_resource_1

AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Liu, Shaoyun Subject: [PATCH] drm/amdgpu/mes: add compatibility checks for set_hw_resource_1 Seems some older MES firmware versions do not properly support this packet. Add back some the compatibility checks. Fixes: f81cd793119e (&qu

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