the VF with sjt version can be initialized and
enabled .
Regards
Shaoyun.liu
-Original Message-
From: Alex Deucher
Sent: Wednesday, August 10, 2022 12:35 PM
To: Liu, Shaoyun
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: use sjt mec fw on aldebaran for sriov
On Fri
[AMD Official Use Only - General]
>From HW point of view , the maximum VF number can reach 16 instead of 12 .
>Although currently no product will use the 16 VFs together, not sure about
>the future.
You can added Acked-by me. I will let Alex & Christion decide whether accept
this change.
[AMD Official Use Only - General]
Looks good to me .
Reviewed-By : shaoyun.liu
-Original Message-
From: Chander, Vignesh
Sent: Thursday, August 18, 2022 1:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kim, Jonathan ; Liu, Shaoyun ;
Chander, Vignesh
Subject: [PATCH] drm/amdgpu: skip
[AMD Official Use Only - General]
Rewed-by: shaoyun liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, November 9, 2022 2:07 PM
To: Wan, Gavin
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Ignore stop rlc on SRIOV environment.
On Wed,
[AMD Official Use Only - General]
I agree with Christian . Although on some hypervisior with live migration
support , there will be specific API between OS and PF driver to handle the
FB content save/restore for VF, in this case , guest side save/restore is not
necessary. On other hyperv
[AMD Official Use Only - General]
Hsakmt has the interfaces for compute user queue. Do we want a unify API for
both graphic and compute ?
Regards
Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Tuesday, January 3, 2023 1:30 PM
To: Sharma, Shashank ;
[AMD Official Use Only - General]
What about the existing rocm apps that already use the hsakmt APIs for user
queue ?
Shaoyun.liu
-Original Message-
From: Alex Deucher
Sent: Tuesday, January 3, 2023 2:22 PM
To: Liu, Shaoyun
Cc: Kuehling, Felix ; Sharma, Shashank
; amd-gfx
Just curious , why the gart range form 0x to 0x1FFF
will cause the engine hang ?
Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Wednesday, October 10, 2018 3:31 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PAT
I'm working on a vm fault issue that this tlb flush type can have
effect on this , do we plan to make a kernel parameter for this ?
Regards
shaoyun.liu
On 2018-10-23 4:37 p.m., Kuehling, Felix wrote:
> It occurred to me that the flush_type is a hardware-specific value, but
> you're using it i
From: shaoyunl
Driver need to call each psp instance to get topology info before set topology
Change-Id: I20d914a0c678686db3f1f99edf250f3656ec9fc1
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
di
;t we also set psp_xgmi_node_info.is_sharing_enabled
> to 1 to enable FB sharing ?
>
> Andrey
>
>
> On 11/08/2018 11:14 AM, Liu, Shaoyun wrote:
>> From: shaoyunl
>>
>> Driver need to call each psp instance to get topology info before set
>> topology
&g
In XGMI configuration, the FB region covers vram region from peer
device, adjust system aperture to cover all of them
Change-Id: I15b14727bbd11f7c2a237fb6ca7b32fb708b2e32
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 6
The doorbell index defines should be compatible with what is used in
windows driver . I don't see the necessary to introduce the new init
file for this instead of use the original MACRO defines. We need to
coordinate with windows driver team for a new user queue SDMA doorbell
range and used
I saw you use the global xgmi_mutex to prevent concurrent reset to be
triggered by different nodes , but after the mutex been released ,
current node may grap the mutex and continue to do another reset .
Maybe we should check the GPU status and skip the reset in this case
since the GPU
Driver shouldn't try to access any GFX registers until RLC is idle.
During the test, it took 12 seconds for RLC to clear the BUSY bit
in RLC_GPM_STAT register which is un-acceptable for driver.
As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK
cycles to finish its critical sectio
The other one i after driver enable the CP interrupt (set register
CP_INT_CNTL_RING0) . I think it still needed but maybe can be moved
under if statement
Regards
shaoyun.liu
On 2018-11-22 12:18 p.m., Kuehling, Felix wrote:
> On 2018-11-22 12:03 p.m., Liu, Shaoyun wrote:
>> Driver
Driver shouldn't try to access any GFX registers until RLC is idle.
During the test, it took 12 seconds for RLC to clear the BUSY bit
in RLC_GPM_STAT register which is un-acceptable for driver.
As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK
cycles to finish its critical sectio
I'm ok with that change .
Regards
shaoyun.liu
On 2018-12-03 3:32 p.m., Kuehling, Felix wrote:
> Shaoyun, FYI
>
>
> Acked-by: Felix Kuehling
>
>
> On 2018-12-03 3:28 p.m., Deucher, Alexander wrote:
>> Acked-by: Alex Deucher
>>
>>
But KFD still need to be notified during reset , the pre_reset call to KFD
will let KFD have a chance to suspend all the running process queues. Was
the reset works normally on SRIOV before the refactor change for XGMI support
? We shouldn't change the logic .
Regards
shaoyun.liu
-O
I see, so ok for me . You can added
Reviewed-by :Shaoyun.liu
-Original Message-
From: Lou, Wentao
Sent: Monday, December 10, 2018 11:54 PM
To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org;
Grodzovsky, Andrey ; Kuehling, Felix
Subject: RE: [PATCH] drm/amdgpu: kfd_pre_reset outside
It seems patch d492c564 revert to this original code otherwise we
shouldn't get the warning . I can add ret = -EINVAL for this.
Regards
shaoyun.liu
On 2019-01-04 6:53 a.m., Dan Carpenter wrote:
> Hello Shaoyun Liu,
>
> The patch fb30fc59a245: "drm/amdgpu : Generate XGMI topology info
> fro
Add message print out and return -EINVAL when driver can not get valid hive
from hive arrary on xgmi configuration
Change-Id: Ic03927904edf0e384b8c4651e19274bb3f2a7d9a
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-
Add message print out and return -EINVAL when driver can not get valid hive
from hive arrary on xgmi configuration
Change-Id: Ic03927904edf0e384b8c4651e19274bb3f2a7d9a
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-
Ping ...
-Original Message-
From: Liu, Shaoyun
Sent: Friday, January 4, 2019 1:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdgpu: Add message print when unable to get valid hive
Add message print out and return -EINVAL when driver can not get valid
I think it's reasonable to use the hive specific lock for hive specific
functions.
The changes is acked-by Shaoyun.liu < shaoyun@amd.com>
-Original Message-
From: amd-gfx On Behalf Of StDenis, Tom
Sent: Monday, January 7, 2019 10:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDeni
Reduce the unnecessary repeat node and hive information during XGMI
initialization
Change-Id: I1c1e4dadf9d771cde53225666b9a10ceca9167c0
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
According to hardware engineer, WTITE_BUST_LENGTH [9:8] in register
SDMA0_CHICKEN_BITS need to change to 3 for better performance
Change-Id: I32121ac19a62c0794b43755078e89d447724bf07
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 d
According to hardware engineer, WRITE_BURST_LENGTH [9:8] in register
SDMA0_CHICKEN_BITS need to change to 3 for better performance
Change-Id: I32121ac19a62c0794b43755078e89d447724bf07
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
1 file changed, 2 insertions(+), 2
When DPM for the specific clock is difabled, driver should still able to
get fix clock info from the pptable
Change-Id: Ic609203b3b87aa75b0cfd57b57717b3bb89daf48
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 16
1 file changed, 16 deletions(-)
When DPM for the specific clock is difabled, driver should still print out
current clock info for rocm-smi support on vega20
Change-Id: I8669c77bf153caa2cd63a575802eb58747151239
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 56 +++---
1 file cha
asic .
Regards
shaoyun.liu
On 2019-02-19 5:20 p.m., Kuehling, Felix wrote:
> On 2019-02-19 4:09 p.m., Liu, Shaoyun wrote:
>> When DPM for the specific clock is difabled, driver should still print out
>> current clock info for rocm-smi support on ve
Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device
Change-Id: I78bdf244da699d2559481ef5afe9663b3e752236
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 35 +-
1
On 2019-02-25 10:50 a.m., Christian König wrote:
> Am 22.02.19 um 22:28 schrieb Liu, Shaoyun:
>> Adjust vram base offset for XGMI mapping when update the PT entry so
>> the address will fall into correct XGMI aperture for peer device
>>
>> Change-Id: I78bdf244da699
On 2019-02-26 2:55 a.m., Christian König wrote:
> Am 25.02.19 um 19:47 schrieb Liu, Shaoyun:
>> On 2019-02-25 10:50 a.m., Christian König wrote:
>>> Am 22.02.19 um 22:28 schrieb Liu, Shaoyun:
>>>> Adjust vram base offset for XGMI mapping when update the PT entry so
&
Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device
Change-Id: I78bdf244da699d2559481ef5afe9663b3e752236
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 ++
1 file changed, 1
Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device
Change-Id: I78bdf244da699d2559481ef5afe9663b3e752236
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +
1 file changed
Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device
Change-Id: I78bdf244da699d2559481ef5afe9663b3e752236
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 +
1 file changed, 9 inse
Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.
Change-Id: I499fb1c389077632fe9cfce4b6dc9a33deff6875
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
Ping
-Original Message-
From: Liu, Shaoyun
Sent: Tuesday, March 5, 2019 11:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdgpu: XGMI pstate switch initial support
Driver vote low to high pstate switch whenever there is an outstanding XGMI
mapping
GC owner suggested the setting should be applied which is missed by HW default
Signed-off-by: shaoyunl
Change-Id: I09dd00c64b88f3d736ec1dd67d544fab597b1c28
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/driv
Hi,
I think even use SDMA to update PTE we may still need to wait the clear
job to be completed if we can not guarantee the clear and set PTE job
will use the exact same SDMA engine ( Did we use a dedicate SDMA engine
for PTE update including clear? ). But if we didn't use the same
engine ,
[AMD Official Use Only - Internal Distribution Only]
ping
-Original Message-
From: Liu, Shaoyun
Sent: Tuesday, March 17, 2020 12:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdgpu/sriov : Don't resume RLCG for SRIOV guest
RLCG is enabled by
[AMD Official Use Only - Internal Distribution Only]
Reviewed by : Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Zhigang Luo
Sent: Tuesday, March 24, 2020 3:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang
Subject: [PATCH] drm/amdgpu: add SOS FW version checking fo
[AMD Official Use Only - Internal Distribution Only]
I didn't calculate the exact required DW used for on e kiq read ( currently
use 32 DW) , That's assume it's right , Can we just alloc 2 more here ? Since
each kiq_read will do the allocation , it won't conflict with other read
operation.
[AMD Official Use Only - Internal Distribution Only]
Hi ,Yintian & Christian
I still don't understand why we need this complicated change here . Why can
not just allocate few more extra space in the ring for each read and use the
space to store the output value ?
Regards
Shaoyun.liu
[AMD Official Use Only - Internal Distribution Only]
I think each kiq operation will call ring_alloc for the package space , why
not just check whether this allocation is succeed or not ?
Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Yintian Tao
Sent: Wednesday, Apri
20 10:52 AM
To: Liu, Shaoyun ; Tao, Yintian ;
Liu, Monk ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: request reg_val_offs each kiq read reg
Hi Shaoyun,
the ring buffer is usually filled with command and not read results.
Allocating extra space would only
-Original Message-
From: Tao, Yintian
Sent: Wednesday, April 22, 2020 11:00 AM
To: Koenig, Christian ; Liu, Shaoyun
; Liu, Monk ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: request reg_val_offs each kiq read reg
Hi Shaoyun
There is one rare corner case
rptr write back to determine the available room in the ring_alloc ?
Regards
Shaoyun.liu
-Original Message-
From: Koenig, Christian
Sent: Wednesday, April 22, 2020 10:57 AM
To: Liu, Shaoyun ; Tao, Yintian ;
Liu, Monk ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [
Sent: Wednesday, April 22, 2020 11:47 AM
To: Tao, Yintian ; Liu, Shaoyun ;
Koenig, Christian ; Liu, Monk ;
Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: request reg_val_offs each kiq read reg
Add more
Especially for the multi-VF environment, we have to
nside function
amdgpu_mm_wreg_mmio_rlc .
Regards
Shaoyun.liu
From: Deucher, Alexander
Sent: Tuesday, May 12, 2020 10:26 AM
To: Tao, Yintian ; Liu, Monk ; Liu,
Shaoyun
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
Subject: Re: [PATCH] drm/amdgpu: turn back rlcg write for gfx_v10
[AMD Publi
Thanks Felix .
We did consider to put the logic into bo_add/bo_rmv, but Felix pointed
out the object can be migrate from FB to system memory after allocation
. I also think of put the logic inside amdgpu_vm_bo_update_mapping ,
but seems that function prefer to take the dma address already
bo with XGMI request ?
Regards
shaoyun.liu
On 2019-03-19 12:09 p.m., Koenig, Christian wrote:
> Am 19.03.19 um 16:42 schrieb Liu, Shaoyun:
>> Thanks Felix .
>>
>> We did consider to put the logic into bo_add/bo_rmv, but Felix pointed
>> out the object can be migrate f
ok , sounds good . Please go ahead to revert the change . I will send
out another one for review .
Regards
shaoyun.liu
On 2019-03-20 6:00 a.m., Christian König wrote:
> Am 19.03.19 um 19:48 schrieb Liu, Shaoyun:
>> As I understand, if we want to implement the logic in b
Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.
Change-Id: I197501f853c47f844055c0e28c0ac00a1ff06607
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
ping
-Original Message-
From: Liu, Shaoyun
Sent: Wednesday, March 20, 2019 4:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdgpu: XGMI pstate switch initial support
Driver vote low to high pstate switch whenever there is an outstanding XGMI
mapping
Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.
Change-Id: I197501f853c47f844055c0e28c0ac00a1ff06607
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_devi
According to HW engineer, they prefer the TMR address be "naturally aligned",
e.g. the start address
must be an integer divide of TME size.
Change-Id: Ie01b3d41e564fc8f416048e001d75edb64c045e3
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +++---
1 file changed, 3 inse
pping.
Regards
Shaoyun.liu
From: amd-gfx on behalf of Kuehling,
Felix
Sent: March 25, 2019 6:28:32 PM
To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: XGMI pstate switch initial support
I don't see any check for the memory type.
-03-26 9:15 a.m., Liu, Shaoyun wrote:
>> I think in a real usage ( tensorflow ex), it's rarely only the
>> system memory (no vram) will be mapped for peer access.
> With that argument you could simplify your change and just power up XGMI
> as soon as a KFD process start
The context device pointer could be different of the object been acctually
allocated
Change-Id: I7b2338858126d75350b65ff04d9bb419e1eae15c
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/a
Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory for
peer device
Change-Id: I1881deff3da19f1f4b58d5765db03a590092a5b2
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
2 files changed, 11
OK , just ignore it . BTW , if you think it's a hack currently used in
KFD to share the memory among GPUs, what's your plane to use the peer
GPU through XGMI from GEM point of view ?
Regards
shaoyun.liu
On 2019-03-26 2:56 p.m., Christian König wrote:
> Am 26.03.19 um 16:5
Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory for
peer device
Change-Id: I1881deff3da19f1f4b58d5765db03a590092a5b2
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
2 files changed,
The next in struct amdgpu_vm_bo_base is not a list_head, I'm not
sure whether we can use list_for_each_entry here.
Regards
shaoyun.liu
On 2019-03-27 3:41 a.m., Christian König wrote:
> Am 26.03.19 um 21:35 schrieb Liu, Shaoyun:
>> Avoid unnecessary XGMI hight pstate trigge
: What's the size of the structure now?
Christian.
Am 27.03.2019 16:22 schrieb "Liu, Shaoyun"
<mailto:shaoyun@amd.com>:
The next in struct amdgpu_vm_bo_base is not a list_head, I'm not
sure whether we can use list_for_each_entry here.
Regards
shaoyun.liu
On 2019-
d so often.
When it grows over the next power of two by this change we need to figure out a
different approach.
Christian.
Am 27.03.2019 16:34 schrieb "Liu, Shaoyun"
<mailto:shaoyun@amd.com>:
you mean struct amdgpu_vm_bo_base ? It only has few pointer and a list_head
XGMI mapping
will be disabled.
Remove the XGMI checking may affect other sharing mechanism.
Shaoyun.liu
On 2019-03-27 11:52 a.m., Kuehling, Felix wrote:
> On 2019-03-26 4:35 p.m., Liu, Shaoyun wrote:
>> Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory
>
Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory for
peer device
Change-Id: I1881deff3da19f1f4b58d5765db03a590092a5b2
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
2 files change
he
loop .
Regards
shaoyun.liu
On 2019-03-28 3:18 p.m., Kuehling, Felix wrote:
> On 2019-03-28 1:55 p.m., Liu, Shaoyun wrote:
>> Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory
>> for peer device
>>
>> Change-Id: I1881deff3da19f1f4b58d5765db03a59
Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory for
peer device
Change-Id: I1881deff3da19f1f4b58d5765db03a590092a5b2
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
2 files change
Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory for
peer device
Change-Id: I1881deff3da19f1f4b58d5765db03a590092a5b2
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
2 files change
Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory for
peer device
Change-Id: I1881deff3da19f1f4b58d5765db03a590092a5b2
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
2 files chang
Avoid unnecessary XGMI hight pstate trigger when mapping none-vram memory for
peer device
Change-Id: I1881deff3da19f1f4b58d5765db03a590092a5b2
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
2 files changed,
On XGMI configuration the ib test may tooks longer to finish
Change-Id: If3afd8eac3c342d32c387804b51fc4a4bdd35d35
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/am
On XGMI configuration the ib test may tooks longer to finish
Change-Id: If3afd8eac3c342d32c387804b51fc4a4bdd35d35
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/dr
On XGMI configuration the ib test may take longer to finish
Change-Id: If3afd8eac3c342d32c387804b51fc4a4bdd35d35
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/dri
Thanks , changed as suggested and pushed
Shaoyun.liu
On 2019-04-03 1:12 p.m., Christian König wrote:
> Am 03.04.19 um 17:42 schrieb Liu, Shaoyun:
>> On XGMI configuration the ib test may tooks longer to finish
>>
>> Change-Id: If3afd8eac3c342d32c387804b51fc4a4bdd35d35
>&
XGMI pstate is controlled by SMU, driver need this interface to communicate
with SMU
Change-Id: I3a30797332557725d48d392bea0c9d59e2d0e427
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 8
2 files chan
Driver need to call SMU to set xgmi pstate
Change-Id: Iad7fd0e3b3155e45be8fe9119686c5bafa3c176c
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drive
ping
On 2019-04-05 12:01 p.m., Liu, Shaoyun wrote:
> XGMI pstate is controlled by SMU, driver need this interface to communicate
> with SMU
>
> Change-Id: I3a30797332557725d48d392bea0c9d59e2d0e427
> Signed-off-by: shaoyunl
> ---
> drivers/gpu/drm/amd/powerplay
XGMI Memory sharing will be disbaled by default for security reason after
boot up, it depends on driver to enable the memory sharing
Change-Id: Ib516066eecfb877f84f1460a4d659abea44adb02
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 d
ping
On 2019-04-08 6:32 p.m., Liu, Shaoyun wrote:
> XGMI Memory sharing will be disbaled by default for security reason after
> boot up, it depends on driver to enable the memory sharing
>
> Change-Id: Ib516066eecfb877f84f1460a4d659abea44adb02
> Signed-off-by: shaoyunl
> ---
&
ping
On 2019-04-05 12:01 p.m., Liu, Shaoyun wrote:
> XGMI pstate is controlled by SMU, driver need this interface to communicate
> with SMU
>
> Change-Id: I3a30797332557725d48d392bea0c9d59e2d0e427
> Signed-off-by: shaoyunl
> ---
> drivers/gpu/drm/amd/powerplay
ping
On 2019-04-05 12:01 p.m., Liu, Shaoyun wrote:
> Driver need to call SMU to set xgmi pstate
>
> Change-Id: Iad7fd0e3b3155e45be8fe9119686c5bafa3c176c
> Signed-off-by: shaoyunl
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 13 -
> 1 file changed
Send message with parameter to SMC to set xgmi pstate
Change-Id: I5d90cffd63690f31f0df62c206b263d300f14234
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
KFD need to provide the info for upper level to determine the data path
Change-Id: Idc809e8f3381b9222dd7be96539522d440f3ee7d
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 +
drivers/gpu/drm/amd/amdgpu/
Upper level runtime need the xgmi hops info to determine the data path
Change-Id: I969b419eab125157e223e9b03980ca229c1e6af4
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 8 ++--
drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 3 ++-
2 files changed, 8 insertions(+), 3 deletions
ping
On 2019-04-17 2:58 p.m., Liu, Shaoyun wrote:
> KFD need to provide the info for upper level to determine the data path
>
> Change-Id: Idc809e8f3381b9222dd7be96539522d440f3ee7d
> Signed-off-by: shaoyunl
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 +
ping .
Felix , can you help check this patch ?
Regards
shaoyun.liu
On 2019-04-17 2:59 p.m., Liu, Shaoyun wrote:
> Upper level runtime need the xgmi hops info to determine the data path
>
> Change-Id: I969b419eab125157e223e9b03980ca229c1e6af4
> Signed-off-by: shaoyunl
> ---
>
comments inline.
On 2019-04-23 2:09 p.m., Kuehling, Felix wrote:
> See inline.
>
> On 2019-04-17 2:58 p.m., Liu, Shaoyun wrote:
>> KFD need to provide the info for upper level to determine the data path
>>
>> Change-Id: Idc809e8f3381b9222dd7be96539522d440f3ee7d
KFD need to provide the info for upper level to determine the data path
Change-Id: Idc809e8f3381b9222dd7be96539522d440f3ee7d
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 +
drivers/gpu/drm/amd/amdgpu/
Upper level runtime need the xgmi hops info to determine the data path
Change-Id: I969b419eab125157e223e9b03980ca229c1e6af4
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 7 +--
drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 3 ++-
2 files changed, 7 insertions(+), 3 deletions(
Adjust the sequence of set/get xgmi topology, so driver can have the latest
XGMI topology info for future usage
Change-Id: I627814f82459a6c9c3d72469f81309488b2a9133
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 32
1 file changed, 20 inse
Here is a list of patches in the topic branch for XGMI support , now I try to
merge them into drm-next .
Please have a look .
Regards
Shaoyun.liu
0001-drm-amd-include-update-the-bitfield-define-for-PF_MA.patch
Description: 0001-drm-amd-include-update-the-bitfield-define-for-PF_MA.patch
00
König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Saturday, September 08, 2018 2:06 PM
To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH 04/12] drm/amdgpu/gmc9: Adjust GART and AGP location with
xgmi offset
Am 07.09.2018 um 22:09 schrieb shaoyunl:
> From: Alex Deucher
52:47 PM
To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/2] drm/amdgpu: fix KIQ ring test fail in TDR of SRIOV
Oh, by the way
>>> Do we know the root cause why this function would ruin MEC ?
Only we call this function right after VF FLR will ruin MEC and lead to
From: Liu, Monk
Sent: December 19, 2019 1:13:24 AM
To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/2] drm/amdgpu: fix KIQ ring test fail in TDR of SRIOV
>>> I would like to check why we need a special sequences for sriov on this
>>> pre_reset. If
Will it looks cleaner if we keep a pre_reset flag in per device structure and
check it in the function when talk to hw?
Regards
Shaoyun.liu
From: Kuehling, Felix
Sent: December 19, 2019 9:21:08 PM
To: amd-gfx@lists.freedesktop.org ; Liu, Monk
; Liu, Shaoyun
Serials are reviewed by : shaoyunl
Looks like a little bit confusing that we have two place for the pte
flags . get_pte_flags already get asic specific mapping flags and
inside amdgpu_vm_bo_split_mapping , driver adjust the real HW mapping
flags again . Maybe better just keep the logic
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