O
Then the user can select the interval they want.
Alex
*From:*amd-gfx
<mailto:amd-gfx-boun...@lists.freedesktop.org> on behalf of
Eric Huang
<mailto:jinhuieri
On 03/30/2018 10:36 AM, Eric Huang wrote:
It is not necessary to do that. The register will reset to 0 after
reading.
The register is not reset after reading. Actually after
PPSMC_MSG_PmStatusLogSample sent, the register will be updated. So it is
still not necessary to do that.
Eric
Eric
update the
registers, we will read out the original value.
Best Regards
Rex
*From:* amd-gfx on behalf of
Eric Huang
*Sent:* Friday, March 30, 2018 11:22 PM
*To:* amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH
Did you contact tools team about this? Since the smc messages
PPSMC_MSG_PmStatusLogStart and PPSMC_MSG_PmStatusLogSample are
exclusively used by tools, driver just shared it. And AGT gets different
result as driver if you change it back to 20ms. To keep consistent
result as AGT, please verify i
Sampling period is too short. The power reading value will be not
aligned with AGT's. It will confuse user that why AMD provides two
different power results.
Regards,
Eric
On 2018-04-04 04:25 AM, Rex Zhu wrote:
1. On polaris10/11/12, Sending smu message PPSMC_MSG_GetCurrPkgPwr to
read cur
ay time is enough unless we got 0 from ixSMU_PM_STATUS_94 .
Best Regards
Rex
*From:* amd-gfx on behalf of
Eric Huang
*Sent:* Wednesday, April 4, 2018 11:36 PM
*To:* amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH 2/
If it is verified by SMU team, I am OK with it.
Regards,
Eric
On 2018-04-11 01:19 PM, Alex Deucher wrote:
On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote:
we don't have limit of [50ms, 4sec] sampling period.
smu calculate average gpu power in real time.
we can read average gpu power through sm
This patch change the power registers reading from average to maximum.
If SMU team verifies it, I am OK with it.
Regards,
Eric
On 2018-04-11 01:21 PM, Alex Deucher wrote:
On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote:
pkgpwr is the average gpu power of 100ms. it is calculated by
firmware in
I am OK with this change.
Regards,
Eric
On 2018-04-11 01:25 PM, Tom St Denis wrote:
On 04/11/2018 01:23 PM, Alex Deucher wrote:
On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote:
This struct can't be used for all asics.
Currently smu only calculate average gpu power in real time.
for vddc/v
This reverts commit b87079ec7b4d38efee015367315958ce5495ba93.
SMU FW team ask to remove this version specific code.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr
Signed-off-by: Eric Huang
Change-Id: I215e49b3cae43c8ba6df0bd40db8b2b07ffc4fed
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr
The fix makes sense to me.
Acked-by: Eric Huang
On 2018-01-11 01:00 PM, Felix Kuehling wrote:
[+Eric]
Acked-by: Felix Kuehling
I'm not familiar with the details of what this does. I'm hoping Eric can
also review this with more power-management experience.
Regards,
Felix
We have min_sclk and min_mclk in previous power profile parameters for
VI, which are similar with min_active_level for Vega10. How to implement
these parameters?
Regards,
Eric
On 2018-01-24 04:37 AM, Rex Zhu wrote:
User can set smu7 profile pamameters through sysfs
echo "0/1/2/3/4">pp_power_
On 2018-01-24 04:37 AM, Rex Zhu wrote:
Change-Id: I4533826ef6e18df125ae4445016873be3b5fe0ce
Signed-off-by: Rex Zhu
---
.../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 104 +
1 file changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris
*From:* amd-gfx on behalf of
Eric Huang
*Sent:* Thursday, January 25, 2018 12:04:55 AM
*To:* amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH 4/4] drm/amd/pp: Implement
set_power_profile_mode on smu7
We have min_sclk and min_mclk in previous
Hi Rex,
Why don't you use function smum_populate_requested_graphic_levels()
which is doing exactly the same thing as the function you add ?
And in old power profile setting function
smu7_set_power_profile_state(), we implement this:
if (hwmgr->chip_id == CHIP_FIJI) {
if (request->ty
meet kfd ‘ s requirement.
Best Regards
Rex
*From:* amd-gfx on behalf of
Eric Huang
*Sent:* Friday, January 26, 2018 12:18:45 AM
*To:* amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH 1/4] drm/amd/pp: Add new smu
Looks good to me. Reviewed-by: Eric Huang
Regards,
Eric
On 07/18/2016 12:59 PM, Rex Zhu wrote:
Change-Id: I68aa5431146b21990a998a777e00139f0478407f
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers
Looks good to me. Reviewed-by: Eric Huang
Regards,
Eric
On 07/18/2016 12:59 PM, Rex Zhu wrote:
Change-Id: I4e09b1c1685657c68a1b4a73928bcaf0ac025d7d
Signed-off-by: Rex Zhu
---
.../powerplay/hwmgr/polaris10_clockpowergating.c | 14 +++--
.../gpu/drm/amd/powerplay/hwmgr
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c4bb4ef..cded082 100644
--- a/drivers/gpu/drm/amd/amdgpu
Hi Tom,
I am concerned with the Sclk Deep Sleep feature. If removing this task,
UVD/VCE will always power on and Sclk deep sleep will not work. And the
power consumption will block our client's Energy start test. So where
are you going to re-add this task ?
Thanks,
Eric
On 16-07-28 10:19 A
Ping ..
On 2025-01-29 10:20, Eric Huang wrote:
In some ASICs L2 cache info may miss in kfd topology,
because the first bitmap may be empty, that means
the first cu may be inactive, so to find the first
active cu will solve the issue.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd
On 2025-02-06 10:14, Lazar, Lijo wrote:
On 1/29/2025 8:50 PM, Eric Huang wrote:
In some ASICs L2 cache info may miss in kfd topology,
because the first bitmap may be empty, that means
the first cu may be inactive, so to find the first
active cu will solve the issue.
Signed-off-by: Eric
, Lijo ; amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH] drm/amdkfd: fix missing L2 cache info in topology
On 2025-02-06 10:14, Lazar, Lijo wrote:
>
> On 1/29/2025 8:50 PM, Eric Huang wrote:
>> In some ASICs L2 cache info may miss in kfd topology,
>> because the first b
On 2025-02-06 22:41, Lazar, Lijo wrote:
On 2/6/2025 10:18 PM, Eric Huang wrote:
I understand your concern. KFD currently only reports one L2 instance,
but not every L2 instance. If customers want to have more detail in all
available L2 info, we probably can change the logic in this function
In some ASICs L2 cache info may miss in kfd topology,
because the first bitmap may be empty, that means
the first cu may be inactive, so to find the first
active cu will solve the issue.
v2: Only find the first active cu in the first xcc
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd
In some ASICs L2 cache info may miss in kfd topology,
because the first bitmap may be empty, that means
the first cu may be inactive, so to find the first
active cu will solve the issue.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 18 --
1 file
nubmer will make the test passed.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index f6aedf69c644..054a78207ffe 100644
--- a
On 2025-03-24 17:21, Alex Deucher wrote:
On Mon, Mar 24, 2025 at 5:07 PM Eric Huang wrote:
On 2025-03-24 15:32, Alex Deucher wrote:
On Mon, Mar 24, 2025 at 1:26 PM Eric Huang wrote:
kfdtest KFDQMTest.OverSubscribeCpQueues with multiple
gpu mode fails on gfx v9.4.3+NPS4+CPX which has 64
On 2025-03-24 15:32, Alex Deucher wrote:
On Mon, Mar 24, 2025 at 1:26 PM Eric Huang wrote:
kfdtest KFDQMTest.OverSubscribeCpQueues with multiple
gpu mode fails on gfx v9.4.3+NPS4+CPX which has 64 gpu
nodes, the queues created are 65x64=4160, but the number
1024 0f
rocm-smi will be able to show the events for KFD process
start/end, it is the implementation of this feature.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_process.c| 4
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 21 +
drivers/gpu/drm/amd/amdkfd
Ping ...
On 2025-04-07 16:52, Eric Huang wrote:
rocm-smi will be able to show the events for KFD process
start/end, it is the implementation of this feature.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_process.c| 4
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
The mistake will lead to NULL kernel oops, so fix it.
Fixes: 56ed4241e9fe ("drm/amdkfd: add smi events for process start and end")
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
SDMA doesn't support oversubsciption, it is the user matter to create
queues over HW limit, but not supposed to be a KFD error.
Signed-off-by: Eric Huang
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 14 --
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
the entries will be appearing at
/sys/kernel/debug/kfd/proc//pasid_.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c | 77
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 5 ++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 3 +
3 files changed, 85
ill
fix the issue.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index c27fd7aec1c3..83d9384ac815 100644
Thanks for the fix, I had the same patch submitted yesterday.
Regards,
Eric
On 2025-04-15 06:44, Dan Carpenter wrote:
The "pdd->drm_priv" NULL check is reversed so it will lead to a NULL
dereference on the next line.
Fixes: 4172b556fd5b ("drm/amdkfd: add smi events for process start and end")
201 - 237 of 237 matches
Mail list logo
