It is to add new option for always keeping gpu mapping.
Signed-off-by: Eric Huang
---
include/uapi/linux/kfd_ioctl.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index fd49dde4d5f4..eba04ebfd9a8 100644
--- a/include/uapi
It is to avoid unnecessary queue eviction when range
is not mapped to gpu.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index
It is to add new option for always keeping gpu mapping.
Signed-off-by: Eric Huang
Change-Id: Iebee35e6de4d52fa29f82dd19f6bbf5640249492
---
include/linux/kfd_ioctl.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/kfd_ioctl.h b/include/linux/kfd_ioctl.h
index 8a0ed49..5c45f58
To improve performance on queue preemption, allocate ctx s/r
area in VRAM instead of system memory, and migrate it back
to system memory when VRAM is full.
Signed-off-by: Eric Huang
Change-Id: If775782027188dbe84b6868260e429373675434c
---
include/hsakmttypes.h | 1 +
src/queues.c
To expose unified memory for ctx save/resotre area feature
availablity to libhsakmt.
Signed-off-by: Eric Huang
---
include/uapi/linux/kfd_ioctl.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index
It is to add new option for always keeping gpu mapping
and bump KFD version for the feature of unified save
restore memory.
Signed-off-by: Eric Huang
Change-Id: Iebee35e6de4d52fa29f82dd19f6bbf5640249492
---
include/linux/kfd_ioctl.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion
To improve performance on queue preemption, allocate ctx s/r
area in VRAM instead of system memory, and migrate it back
to system memory when VRAM is full.
Signed-off-by: Eric Huang
Change-Id: If775782027188dbe84b6868260e429373675434c
---
include/hsakmttypes.h | 1 +
src/queues.c
*From:* amd-gfx on behalf of
Eric Huang
*Sent:* Monday, July 11, 2022 2:41 PM
*To:* amd-gfx@lists.freedesktop.org
*Cc:* Huang, JinHuiEric ; Kuehling, Felix
*Subject:* [PATCH] drm/amdkfd: bump KFD version for unified ctx
save/restore memory
To
dmabuf is allocated/mapped as GTT domain, when dma-unmapping dmabuf
changing placement to CPU will trigger memory eviction after calling
ttm_bo_validate, and the eviction will cause performance drop.
Keeping the correct domain will solve the issue.
Signed-off-by: Eric Huang
---
drivers/gpu/drm
odule param.
Regards,
Felix
Am 2023-04-03 um 13:59 schrieb Eric Huang:
dmabuf is allocated/mapped as GTT domain, when dma-unmapping dmabuf
changing placement to CPU will trigger memory eviction after calling
ttm_bo_validate, and the eviction will cause performance drop.
Keeping the correct
pecial case in the above if-block for old_mem->mem_type ==
AMDGPU_PL_PREEMPT: use amdgpu_bo_sync_wait with
owner=AMDGPU_FENCE_OWNER_KFD so that it doesn't wait for eviction
fences
Regards,
Felix
Am 2023-04-04 um 10:36 schrieb Eric Huang:
Here is the backtrace from Jira:
Thu Nov 10 13:10:23 2022]
LE in the imported DMABuf BO.
On 2023-04-10 14:28, Eric Huang wrote:
Hi Felix,
Thanks for your review and suggestion, but unfortunately the
AMDGPU_GEM_DOMAIN_PREEMPTIBLE is not defined in amdgpu_drm.h. I
understand we need the memory eviction on either
kfd_mem_dmamap_dmabuf
It is to avoid redundant eviction for KFD's DMAbuf import
bo when dmaunmapping DMAbuf. The DMAbuf import bo has
been set as AMDGPU_PL_PREEMPT in KFD when mapping.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 -
1 file changed, 4 insertions(+), 1 del
It is to avoid redundant eviction for KFD's DMAbuf import
bo when dmaunmapping DMAbuf. The DMAbuf import bo has
been set as AMDGPU_PL_PREEMPT in KFD when mapping.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 ++-
1 file changed, 6 insertions(+), 1 del
Hi Christian,
What do you think about Felix's explanation?
Regards,
Eric
On 2023-04-13 09:28, Felix Kuehling wrote:
Am 2023-04-13 um 07:35 schrieb Christian König:
Am 13.04.23 um 03:01 schrieb Felix Kuehling:
Am 2023-04-12 um 18:25 schrieb Eric Huang:
It is to avoid redundant evictio
-26 9:03, Christian König wrote:
Am 25.04.23 um 16:11 schrieb Eric Huang:
Hi Christian,
What do you think about Felix's explanation?
That's unfortunately not something we can do here.
Regards,
Eric
On 2023-04-13 09:28, Felix Kuehling wrote:
Am 2023-04-13 um 07:35 schrieb Chr
ian König wrote:
Am 26.04.23 um 18:58 schrieb Felix Kuehling:
On 2023-04-26 9:03, Christian König wrote:
Am 25.04.23 um 16:11 schrieb Eric Huang:
Hi Christian,
What do you think about Felix's explanation?
That's unfortunately not something we can do here.
Regards,
Eric
On 2023-0
On 2023-04-28 12:41, Felix Kuehling wrote:
On 2023-04-28 10:17, Eric Huang wrote:
On 2023-04-27 23:46, Kuehling, Felix wrote:
[AMD Official Use Only - General]
Re-mapping typically happens after evictions, before a new eviction
fence gets attached. At that time the old eviction fence
On 2023-04-28 15:42, Felix Kuehling wrote:
On 2023-04-28 14:09, Eric Huang wrote:
On 2023-04-28 12:41, Felix Kuehling wrote:
On 2023-04-28 10:17, Eric Huang wrote:
On 2023-04-27 23:46, Kuehling, Felix wrote:
[AMD Official Use Only - General]
Re-mapping typically happens after evictions
Reviewed-by: Eric Huang
Regards,
Eric
On 2023-05-01 16:52, Felix Kuehling wrote:
Don't move DMABuf attachments for PCIe P2P mappings to the SYSTEM domain
when unmapping. This avoids triggering eviction fences unnecessarily.
Instead do the move to SYSTEM and back to GTT when mapping
Eric Huang (1):
drm/amdkfd: add xcc instance for debugger APIs
Jonathan Kim (4):
drm/amdgpu: add debugger support for GC v9.4.3
drm/amdkfd: add multi-process debugging support for GC v9.4.3
drm/amdkfd: restore debugger additional info for gfx v9_4_3
drm/amdkfd: enable watch points
Acked-by: Amber Lin
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 10 --
drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 +++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/
device initialization.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
b/drivers/gpu/drm/amd/amdkfd
Since GFX9 GPU has multiple xcc instances, this is to
implement this change in KFD for debugger APIs.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 6 --
drivers/gpu/drm/amd/amdgpu
From: Jonathan Kim
Implement the similarities as GC v9.4.2, and the difference
for GC v9.4.3 HW spec.
Signed-off-by: Jonathan Kim
Signed-off-by: Eric Huang
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 7 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h | 30
.../drm/amd/amdgpu
From: Jonathan Kim
Set watch points for all xcc instances on GFX943.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Signed-off-by: Eric Huang
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 6 --
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 16 ++--
2
.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index db772942f7a6..fb1bb593312e 100644
--- a
The point bo->kfd_bo is NULL for queue's write pointer BO
when creating queue on mGPU. To avoid using the pointer
fixes the error.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
There will be data corruption on vram allocated by svm
if initialization is not being done. Adding sync is to
resolve this issue.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b
Ping.
On 2023-01-05 14:28, Eric Huang wrote:
The point bo->kfd_bo is NULL for queue's write pointer BO
when creating queue on mGPU. To avoid using the pointer
fixes the error.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu
From: Jay Cornwall
Based on gfx10 with following changes:
- GPR_ALLOC.VGPR_SIZE field moved (and size corrected in gfx10)
- s_sendmsg_rtn_b64 replaces some s_sendmsg/s_getreg
- Buffer instructions no longer have direct-to-LDS modifier
Signed-off-by: Jay Cornwall
Reviewed-by: Laurent Morichetti
It is to simplify trap handler support for new asics in
the future.
Signed-off-by: Eric Huang
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 2527 +
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 325 ++-
.../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 244 +-
3 files
Most of changes are for debugger feature, and it is
to simplify trap handler support for new asics in the
future.
Signed-off-by: Eric Huang
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 2527 +
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 325 ++-
.../drm/amd/amdkfd
Does it break the case of q->gws with q->properties.is_active == true?
Regards,
Eric
On 2022-06-15 17:56, Philip Yang wrote:
We remove the user queue from MES scheduler to update queue properties.
If the queue becomes active after updating, add the user queue to MES
scheduler, to be able to han
Reviewed-by: Eric Huang
On 2022-06-17 15:26, Philip Yang wrote:
This reverts commit 8b9aa1fa82baf4e8b6a2daa3aa4d69b728df727e.
As it breaks pqm_set_gws.
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers
From: Jonathan Kim
Implement the similarities as GC v9.4.2, and the difference
for GC v9.4.3 HW spec.
Signed-off-by: Jonathan Kim
Signed-off-by: Eric Huang
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 7 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h | 30
.../drm/amd/amdgpu
Acked-by: Amber Lin
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 10 --
drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 +++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/
From: Jonathan Kim
Set watch points for all xcc instances on GFX943.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Signed-off-by: Eric Huang
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 6 --
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 16 ++--
2
device initialization.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
b/drivers/gpu/drm/amd/amdkfd
Eric Huang (1):
drm/amdkfd: add xcc instance for debugger APIs
Jonathan Kim (4):
drm/amdgpu: add kfd2kgd debugger callbacks for GC v9.4.3
drm/amdkfd: restore debugger additional info for gfx v9_4_3
drm/amdkfd: enable watch points globally for gfx943
drm/amdkfd: add multi-process
Since GFX9 GPU has multiple xcc instances, this is to
implement this change in KFD for debugger APIs.
Signed-off-by: Eric Huang
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c| 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 6 --
drivers/gpu/drm/amd/amdgpu
Eric Huang (2):
drm/amdkfd: enable grace period for xcc instance
drm/amdkfd: always keep trap enabled for GC v9.4.3
Jonathan Kim (4):
drm/amdkfd: add kfd2kgd debugger callbacks for GC v9.4.3
drm/amdkfd: restore debugger additional info for gfx v9_4_3
drm/amdkfd: enable watch points
From: Jonathan Kim
Implement the similarities as GC v9.4.2, and the difference
for GC v9.4.3 HW spec, i.e. xcc instance.
Signed-off-by: Jonathan Kim
Signed-off-by: Eric Huang
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 10 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h | 30
device initialization.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
b/drivers/gpu/drm/amd/amdkfd
To set TTMP setup on by default.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 +++---
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm
Acked-by: Amber Lin
Signed-off-by: Eric Huang
Reviewed-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 10 --
drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 +++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/d
From: Jonathan Kim
Set watch points for all xcc instances on GFX943.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd
each xcc instance needs to get iq wait time and set
grace period accordingly.
Signed-off-by: Eric Huang
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 9 --
.../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +-
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 32
instance needs to get iq wait time and set
grace period accordingly.
Signed-off-by: Eric Huang
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 9 --
.../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +-
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 32 +++
.../drm
time and set
grace period accordingly.
Signed-off-by: Eric Huang
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 9 --
.../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +-
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 32 +++---
-
.../drm/amd/amdkfd
Jonathan Kim (4):
drm/amdkfd: add kfd2kgd debugger callbacks for GC v9.4.3
drm/amdkfd: restore debugger additional info for gfx v9_4_3
drm/amdkfd: enable watch points globally for gfx943
drm/amdkfd: add multi-process debugging support for GC v9.4.3
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebar
Acked-by: Amber Lin
Signed-off-by: Eric Huang
Reviewed-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 10 --
drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 +++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/d
From: Jonathan Kim
Implement the similarities as GC v9.4.2, and the difference
for GC v9.4.3 HW spec, i.e. xcc instance.
Signed-off-by: Jonathan Kim
Signed-off-by: Eric Huang
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 8 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h | 27
device initialization.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Signed-off-by: Eric Huang
Reviewed-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h
b/drivers
From: Jonathan Kim
Set watch points for all xcc instances on GFX943.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
Signed-off-by: Eric Huang
Reviewed-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff
d the difference
for GC v9.4.3 HW spec, i.e. xcc instance.
Signed-off-by: Jonathan Kim
Signed-off-by: Eric Huang
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 8 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h | 27 +++
.../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 166 +-
..
Read/write grace period from/to first xcc instance of
xcp in kfd node.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 11 ---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c| 10
OK. Mukul, I will resend this patch based on top of yours.
Regards,
Eric
On 2023-07-10 18:24, Joshi, Mukul wrote:
[AMD Official Use Only - General]
-Original Message-
From: amd-gfx On Behalf Of Eric
Huang
Sent: Monday, July 10, 2023 3:46 PM
To: amd-gfx@lists.freedesktop.org
Cc
Read/write grace period from/to first xcc instance of
xcp in kfd node.
Signed-off-by: Eric Huang
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 21 ---
.../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +-
.../drm/amd/amdkfd/kfd_packet_manager_v9.c| 8 ---
3 files
On 2023-07-11 14:38, Felix Kuehling wrote:
On 2023-07-11 10:28, Eric Huang wrote:
Read/write grace period from/to first xcc instance of
xcp in kfd node.
Signed-off-by: Eric Huang
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 21 ---
.../drm/amd/amdkfd
To setup ttmp on as default for gfx v9.4.3 in IP hw init.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 86a84a0970f0
in a safe manner.
Signed-off-by: Jonathan Kim
Reviewed-by: Eric Huang
Regards,
Eric
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 13 -
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 19 +--
driver
solution is to clear the register as gfx v9 in KFD.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
b/drivers/gpu/drm/amd/amdgpu
Kuehling
On 2023-08-10 16:47, Eric Huang wrote:
KFD currently relies on MEC FW to clear tcp watch control
register by sending MAP_PROCESS packet with 0 of field
tcp_watch_cntl to HWS, but if the queue is suspended, the
packet will not be sent and the previous value will be
left on the register
lowing apps.
So the solution is to clear the register as gfx v9 in KFD.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
b/driv
rt of Jon's debugger upstreaming patch series? Or did
this come later? This patch only enables the workaround for v9.4.2.
Regards,
Felix
On 2023-08-10 17:52, Eric Huang wrote:
The problem is the queue is suspended before clearing address watch
call in KFD, there is not queue preemption
7;s debugger upstreaming patch series? Or did
this come later? This patch only enables the workaround for v9.4.2.
Regards,
Felix
On 2023-08-10 17:52, Eric Huang wrote:
The problem is the queue is suspended before clearing address watch
call in KFD, there is not queue preemption and queue resu
On 2023-08-11 09:26, Felix Kuehling wrote:
Am 2023-08-10 um 18:27 schrieb Eric Huang:
There is not UNMAP_QUEUES command sending for queue preemption
because the queue is suspended and test is closed to the end.
Function unmap_queue_cpsch will do nothing after that.
How do you suspend queues
It fixes cpu stuck issue in some extreme test cases.
Reviewed-by: Eric Huang
On 2019-12-12 9:51 a.m., Philip Yang wrote:
Because queue_work schedule the work on the same CPU the interrupt
handler is running, if there are many interrupts pending, it takes
longer time for work queue to start
SDMA MQD memory type is NC that causes MQD data overwritten
accidentally by an old stable cache line. Changing it to UC
default for GART will fix the issue.
Change-Id: If609f47c78cb97e2c8dc930df2ab5c10c29dfe56
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
Reviewed-by: Eric Huang
On 2017-05-16 10:42 AM, Dan Carpenter wrote:
Smatch complains about a signedness bug here:
vega10_hwmgr.c:4202 vega10_force_clock_level()
warn: always true condition '(i >= 0) => (0-u32max >= 0)'
Fixes: 7b52db39a4c2 ("drm/amd
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 33 ++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index a7c5bf7..267e077 100644
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 3 +++
drivers/gpu/drm/amd/include/cgs_common.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 53d1591..c316f8f 100644
--- a
Change to more meaningful range that triggers thermal
interrupts.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
b/drivers/gpu/drm
Eric Huang (4):
drm/amdgpu: add cgs query info of pci bus devfn
drm/amd/powerplay: add register thermal interrupt in hwmgr_hw_init
drm/amd/powerplay: implement register thermal interrupt for Vega10
drm/amd/powerplay: change alert temperature range
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 75 -
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 6 +++
2 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
b/drivers/gpu/drm/amd
Setting package power PID to 1 fixes performance drop caused by
updated SMU FW, before DPM is enabled.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b
Setting package power PID to 1 fixes performance drop caused by
updated SMU FW, before DPM is enabled.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
Eric Huang (2):
drm/amd/powerplay: add one smc message for Vega10
drm/amd/powerplay: fix performance drop on Vega10
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 ++
drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 3 ++-
2 files changed, 8 insertions(+), 1 deletion
This is used to fix performance drop caused by updated SMU FW.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
b/drivers/gpu/drm/amd/powerplay
Ping.
On 2017-10-19 03:14 PM, Eric Huang wrote:
Eric Huang (2):
drm/amd/powerplay: add one smc message for Vega10
drm/amd/powerplay: fix performance drop on Vega10
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 ++
drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 3
ASIC temperature reading from HOTSPOT to ASIC edge.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
b/drivers/gpu/drm/amd/powerplay
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d4ff742..9d3bdad 100644
--- a/drivers/gpu/drm/amd/powerplay
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 6 ++
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 3 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr
PSP will disable legacy mmhub PG setting that is programming
registers, and drive will use SMC message to
set it up.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 4
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 3 +++
drivers/gpu/drm/amd/include
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 22 ++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay
Yes. SMU only provides enabling message.
Thanks,
Eric
On 2018-02-06 03:50 PM, Deucher, Alexander wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Eric Huang
Sent: Tuesday, February 6, 2018 3:41 PM
To: amd-gfx@lists.freedesktop.org
Cc
Again, it still has risk when updating smc table without calling
smu7_freeze/unfreeze_sclk_mclk_dpm().
Regards,
Eric
On 2018-02-08 04:14 AM, Rex Zhu wrote:
Change-Id: I4533826ef6e18df125ae4445016873be3b5fe0ce
Signed-off-by: Rex Zhu
---
.../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 1
On 2018-02-08 11:35 AM, Zhu, Rex wrote:
>But in auto mode, we may want to force a particular profile within the
>driver for a specific use case. E.g., for VR, we may want to select
>the VR profile when the user sets the priority to high in the context
>ioctl, and then switch it back to autowa
ile or custom profile.
set clock range. and set auto dpm mode, switch back
Best Regards
Rex
*From:* amd-gfx on behalf of
Eric Huang
*Sent:* Friday, February 9, 2018 12:47 AM
*To:* amd-gfx@lists.freedesktop.org
The series: Reviewed-by: Eric Huang
On 2018-02-13 02:46 PM, Alex Deucher wrote:
The logic has moved to cgs. mclk switching with DC at higher refresh
rates should work.
Signed-off-by: Alex Deucher
Cc: Harry Wentland
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
1 file
a bug in programming thermal interrupt register masks out
interrupts and driver cannot receive interrupts. Setting
0 to mask bits will fix it.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
As I mentioned in code review for new power profile, old gfx/compute
power profile have two scenarios for auto switching. One is
gfx->compute(default)->gfx and other is gfx->compute(custom)->gfx. New
power profile only satisfies first one, but in second one for user
debugging, user setting of p
Yes. That is a solution.
Eric
On 2018-02-27 11:27 AM, Alex Deucher wrote:
On Tue, Feb 27, 2018 at 11:22 AM, Eric Huang wrote:
As I mentioned in code review for new power profile, old gfx/compute power
profile have two scenarios for auto switching. One is
gfx->compute(default)->gfx and
power containment disabled only on Fiji and compute
power profile. It violates PCIe spec and may cause power
supply failed. Enabling it will fix the issue, even the
fix will drop performance of some compute tests.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
Reviewed-by: Eric Huang
On 2018-03-02 12:53 PM, Kent Russell wrote:
kstrtol can handle negative values, which is unchecked here. While
setting a negative value will result in the mask being 1<<0x ,
which the SMU will ignore because it's out of long bits, return an
error
Deucher
Signed-off-by: Alex Deucher
The theoretical sampling period is from 50ms to 4sec, original 2sec
is long but correct, and 20ms is too short. change it to more
reasonable 200ms.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 ++-
1 file changed, 2
Alex
*From:* amd-gfx on behalf of
Eric Huang
*Sent:* Thursday, March 29, 2018 3:21:52 PM
*To:* amd-gfx@lists.freedesktop.org
*Cc:* Huang, JinHuiEric
*Subject:* [PATCH] drm/amd/powerply: fix power reading on Fiji
Power value is wrong report
nt.
Alex
*From:* amd-gfx
<mailto:amd-gfx-boun...@lists.freedesktop.org> on behalf of Eric
Huang <mailto:jinhuieric.hu...@amd.com>
*Sent:* Thursday, March 29, 2018 3:21:52 PM
*To:* amd-gfx@lists.freedesktop.org
<mailto:amd-gfx@li
It is not necessary to do that. The register will reset to 0 after reading.
Eric
On 03/30/2018 03:33 AM, Rex Zhu wrote:
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerpl
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