Re: amdgpu display corruption and hang on AMD A10-9620P

2017-06-12 Thread Carlo Caione
1fcd83f0 [ 80.766913] R10: 000b R11: 0246 R12: 55f51fcd9ff0 [ 80.766915] R13: 0007 R14: 7fa5261297b8 R15: 2710 [ 80.766931] Kernel Offset: 0x2280 from 0x8100 (relocation range: 0x8000-0xbff

Re: amdgpu display corruption and hang on AMD A10-9620P

2017-06-15 Thread Carlo Caione
On Mon, Jun 12, 2017 at 12:24 PM, Carlo Caione wrote: > On Tue, May 9, 2017 at 7:03 PM, Deucher, Alexander > wrote: >>> -Original Message- >>> From: Daniel Drake [mailto:dr...@endlessm.com] >>> Sent: Tuesday, May 09, 2017 12:55 PM >>> To: dri-dev

[PATCH] Audio output doesn't work on HDMI and DP ports of my MSI RX 460 2G OC.

2017-09-11 Thread Carlo Caione
From: Jan Andres The line in question seems to assume some kind of correlation between the numbering of the audio converters and the stream encoders, which doesn't exist on my card: Here, the active stream encoders are indexed 2 and 3 while audios have index 0 and 1, so audio never comes up. I c

[PATCH 4.15 1/4] drm/amd/display: Adding DCN1 registers

2018-01-03 Thread Carlo Caione
From: Mikita Lipski Registers added to definition list that are required for multi display synchronization Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_timing_generator.h | 33 ++

[PATCH 4.15 0/4] Backport DC commits to fix display corruption

2018-01-03 Thread Carlo Caione
From: Carlo Caione Hi, on several laptops [0] we are seeing display corruption when using multiple / external displays. We already opened an issue upstream [1]. The following 4 patches are taken from agd5f/amd-staging-drm-next and they seem able to solve the issue. Can those be included in 4.15

[PATCH 4.15 2/4] drm/amd/display: Multi display synchronization logic

2018-01-03 Thread Carlo Caione
From: Mikita Lipski This feature synchronizes multiple displays with various timings to a display with the highest refresh rate it is enabled if edid caps flag multi_display_sync is set to one There are limitations on refresh rates allowed that can be synchronized. That would prevent from underf

[PATCH 4.15 4/4] drm/amd/display: Change frontend/backend programming sequence

2018-01-03 Thread Carlo Caione
From: "Leo (Sunpeng) Li" This is a follow-up to the following change: Yongqiang Sun: Program front end first when set mode. Due to pipe-splitting features, how we handle stream enabling and disabling needs to change. In the case of pipe split disable, two planes need to be combined back into t

[PATCH 4.15 3/4] drm/amd/display: Both timing_sync and multisync need stream_count > 1

2018-01-03 Thread Carlo Caione
From: Harry Wentland Previous code threw a warning about misleading indentation Signed-off-by: Harry Wentland Reviewed-by: Mikita Lipski Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

Re: [PATCH 4.15 0/4] Backport DC commits to fix display corruption

2018-01-03 Thread Carlo Caione
On Wed, Jan 3, 2018 at 5:32 PM, Harry Wentland wrote: > On 2018-01-03 12:11 PM, Carlo Caione wrote: >> From: Carlo Caione >> >> Hi, >> on several laptops [0] we are seeing display corruption when using multiple / >> external displays. We already opened an issue

Re: AMD DC test results

2018-01-10 Thread Carlo Caione
eers, [0] https://www.spinics.net/lists/dri-devel/msg161258.html -- Carlo Caione | +44.7384.69.16.04 | Endless ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx