This DC patchset brings improvements in multiple areas. In summary, we have:
- FW promotion to 0.0.95
- DSC fixes for supported Docks
- Fixes eDP display issue
- Vendor LTTR workarounds
- Fixes Tiled display audio issue
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.95
Aric Cyr (
From: Stylon Wang
[Why + How]
Enable P010 for SDR video applications.
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Bhawanpreet Lakha
Acked-by: Bhawanpreet Lakha
Signed-off-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc
arded by a CONFIG
that cannot be set by the user and shouldn't need to be.
Check for specific branch device IDs to device whether to enable
the workaround for multiple display scenarios.
Reviewed-by: Hersen Wu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Nicholas Kazlauskas
---
.../display
.
Reviewed-by: Jun Lei
Reviewed-by: Mustapha Ghaddar
Acked-by: Bhawanpreet Lakha
Signed-off-by: meenakshikumar somasundaram
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 35 +++-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 54 +++
drivers/gpu/drm/amd/display/dc/dc.h
From: Dale Zhao
[Why]
Using the hdmi_disable option doesnt disable 6GB bandwidth
[How]
Add debug.hdmi20_disable flage when checking 6GB enable or not.
Reviewed-by: Chris Park
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Signed-off-by: Dale Zhao
---
drivers/gpu/drm/amd/display/dc/dce
-by: Bhawanpreet Lakha
Signed-off-by: Brandon Syu
---
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110
values changed.
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
Signed-off-by: Mustapha Ghaddar
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core
From: Evgenii Krasnikov
[HOW&WHY]
Add function to be used for early eDP power on
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
Signed-off-by: Evgenii Krasnikov
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 11 +++
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
From: Michael Strauss
[WHY]
Allow changing DET size with debug flag for testing purposes
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dc.h | 12
.../gpu/drm/amd/display/dc/dcn31
on a USB4 dock is set
during detection of the dock and only cleared when the USB4 dock is
disconnected.
Reviewed-by: Jun Lei
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 16 +++
.../gpu/drm/amd
From: Anthony Koo
Signed-off-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
Reviewed-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd
From: George Shen
[Why]
Certain display configurations require an extra delay before
reading lane status with certain LTTPR.
[How]
Add temporary workaround to force AUX RD interval to
16ms for CR and EQ. Needs to be refactored later.
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
Signed
Kazlauskas
Acked-by: Bhawanpreet Lakha
Signed-off-by: Mikita Lipski
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 44 +++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm
Acked-by: Bhawanpreet Lakha
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 44 +++
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
2 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core
From: Aric Cyr
This version brings along the following:
- FW promotion to 0.0.95
- DSC fixes for supported Docks
- Fixes eDP display issue
- Vendor LTTR workarounds
- Fixes Tiled display audio issue
Signed-off-by: Aric Cyr
Acked-by: Bhawanpreet.Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h |
From: "Shen, George"
[Why]
VS and PE requested by repeater should not persist for the sink.
[How]
Clear DPCD lane settings after repeater link training finishes.
Reviewed-by: Wesley Chalmers
Acked-by: Bhawanpreet Lakha
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/displ
From: George Shen
[Why]
Certain LTTPR require special workarounds in order to comply
with DP specifications.
[How]
Implement vendor specific sequences via DPCD writes to
vendor-specific LTTPR registers.
Reviewed-by: Jun Lei
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by
call psp_int_ta_microcode() to parse the ta firmware.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index
This field is not defined for DCN3
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 1 +
.../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 22 +++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
[Why]
In certain cases the crtc can be NULL and returning -EINVAL causes
atomic check to fail when it shouln't. This leads to valid
configurations failing because atomic check fails.
[How]
Don't early return if crtc is null
Signed-off-by: Bhawanpreet Lakha
---
drive
Without this, enabling dsc will cause a nullptr
Reviewed-by: Mikita Lipski
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd
dpcs reg are missing for dcn3 link encoder regs list, so add them.
Also remove
DPCSTX_DEBUG_CONFIG and RDPCSTX_DEBUG_CONFIG as they are unused and
cause compile errors for dcn3
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h | 2 --
drivers/gpu
ff-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
index d3192b9d0c3d..47f8ee2832ff 100644
new surface
programming behaviour")
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
in
From: Dmytro Laktyushkin
At the moment on flip opp reassignment does not work in all cases
for non root pipes.
This change simply makes sure we prefer pipes not used previously
when splitting in dcn3.
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc
;)
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 61 +++
1 file changed, 49 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/displa
These function pointers are missing from dcn30_init
.calc_vupdate_position
.set_pipe
So add them
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
b
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/dcn302/dcn302_resource.c | 58 +--
1 file changed, 1 insertion(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index
Some setups will fail to build. So copy dcn301 makefile setup
which is known to work
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn302/Makefile| 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
b
s for linux
(MALL stutter)")
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_
: 06d5652541c3 ("drm/amd/display: enable idle optimizations for linux
(MALL stutter)")
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/g
DCN
Fixes: 06d5652541c3 ("drm/amd/display: enable idle optimizations for linux
(MALL stutter)")
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/a
There is some missing mall code, this series updates the code.
-enable watermark programming
-dynamic cursor cache
-updates to mall eligibility check
Bhawanpreet Lakha (3):
drm/amd/display: Enable programing of MALL watermarks
drm/amd/display: Dynamic cursor cache size for MALL eligibility
uncomment watermark set d
Signed-off-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc
[Why]
Currently we use the maximum possible cursor cache size when deciding if we
should attempt to enable MALL, but this prevents us from enabling the
feature for certain key use cases.
[How]
- consider cursor bpp when calculating if the cursor fits
Signed-off-by: Bhawanpreet Lakha
Signed-off
Update the function for idle optimizations
-remove hardcoded size
-enable no memory-request case
-add cursor copy
-update mall eligibility check case
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Joshua Aberback
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../drm/amd/display
From: Harry Wentland
[Why]
DC needs to communicate with PM FW through GPU memory. In order
to do so we need to be able to allocate memory from within DC.
[How]
Call amdgpu_bo_create_kernel to allocate GPU memory and use a
list in amdgpu_display_manager to track our allocations so we
can clean th
[Why]
The dm struct is only being used if DCN config is defined and this
causes a unused variable warning if DCN option is not set.
[How]
Remove the compile flag so the variable is used (there also seems to be
a duplicate guard due to a bad rebase) so remove the outer guard to fix
the warning.
Fi
interrupts
resume
-Edit cached state to force full update
-Commit cached state from suspend
-Build stream and plane updates from the cached state
-Commit stream/plane updates
-Enable interrupts
-Release DC lock
Signed-off-by: Bhawanpreet Lakha
-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 182 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
2 files changed, 182 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd
From: Alvin Lee
Get the values from VBIOS table
Signed-off-by: Alvin Lee
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/bios/bios_parser2.c| 98 +++
.../gpu/drm/amd/display/dc/dc_bios_types.h| 1 +
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 7
This mask is missing for dcn3 so add it from dcn20.
enc2_set_dynamic_metadata() trys to sets this and we get a
generic_reg warning since the mask is not defined.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h | 1 +
1 file changed, 1
call psp_int_ta_microcode() to parse the ta firmware.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 423386272920
[Why]
Currently navy_flounder is using sienna_cichlid_dmcub.bin.
[How]
Create a seperate define so navy_flounder will use its own firmware.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
Use DCN21 functions instead of DCE110
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
b/drivers/gpu/drm/amd/display/dc/dcn30
Use the same case as sienna_cichlid
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index d488d250805d..e16874f30d5d
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2b0a2b93994b..74cbaf212698 100644
--- a/drivers/gpu/drm/amd
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 03e88dbf92be..edd2d6bd1d86 100644
--- a/drivers/gpu
ned-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 43 +++
1 file changed, 6 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index b3
There is a delta in the dmub code
- add boot options
- add boot status
- remove unused auto_load_is_done func pointer
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 20 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
.../gpu/drm/amd
to keep track of when to enable or
disable HDCP
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Zhan Liu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 +++
2 files changed, 14 insertions(+), 4 deletions(-)
diff
[Why]
These comments are helpful in understanding which case each if
statement handles.
[How]
Add comments for state transitions (9 possible cases)
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Zhan Liu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +--
1 file changed
dpcs reg are missing for dcn302 link encoder regs list, so add them.
Just like dcn3
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers
From: Joshua Aberback
[How]
- use dc interface instead of hwss interface in cursor functions, to keep
dc->idle_optimizations_allowed updated
- add dc interface to check if idle optimizations might apply to a plane
Change-Id: I130107b6428b4afd73a1a177ef0f8125e0d877e6
Signed-off-by: Joshua Aberb
: Ib1e14a84ee2e8c6e057072128693449665012584
Signed-off-by: Bhawanpreet Lakha
Acked-by: Alex Deucher
Reviewed-by: Nick Kazlauskas
---
drivers/gpu/drm/amd/display/Kconfig | 6 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 +++
.../gpu/drm/amd/display/amdgpu_dm
From: Joshua Aberback
We need these to support PSR on DCN302
Signed-off-by: Joshua Aberback
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302
arios.
Regards,
Bhawan
Bhawanpreet Lakha (6):
drm/amd/display: Add structs for Freesync Panel Replay
drm/amd/display: Add Functions to enable Freesync Panel Replay
drm/amd/display: Add Freesync Panel DM code
drm/amd/display: Read replay data from sink
drm/amd/display: Enable Repla
e and Sink remaining timing synchronized, Replay can be activated
in more UI scenarios.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 +
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 29 ++
drivers/gpu/drm/amd/display/dc/dc_types.h | 41 ++
.../gp
Read DP_SINK_PR_PIXEL_DEVIATION_PER_LINE and
DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/link/protocols/link_dp_capability.c | 10 ++
drivers/gpu/drm/amd/display/include/dpcd_defs.h| 4 +++-
2 files changed, 13 insertions
Add various functions for replay, such as construct, destroy, enable
get_state, and copy_setting etc. These functions communicate with the
firmware to setup and enable panel replay
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +-
.../gpu/drm/amd
- Setup replay config on device init.
- Enable replay if feature is enabled and psr is not going to be enabled
- Add debug masks to enable replay on supported ASICs
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +++
.../amd/display
We need certain conditions for replay to be enabled, so create an
interface in DM to enable/disable replay.
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_replay.c | 183 ++
.../amd/display
We need to make sure that the panel supports replay.
This info is inside the amd vsdb (vendor specific data block). Create a
function to parse the block and read the replay_mode bit.
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37
tion conditions.
Reviewed-by: Wenjing Liu
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_r
From: Bhawanpreet Lakha
[Why]
we save the prev_dppclk value using "dpp_inst" but when reading this
value we use the index "i". In a case where a pipe is fused off we can
end up reading the incorrect instance because i != dpp_inst in this
case.
[How]
read the prev_dppclk us
e and Sink remaining timing synchronized, Replay can be activated
in more UI scenarios.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 4 +
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 29 ++
drivers/gpu/drm/amd/display/dc/dc_types.h | 41 ++
.../dr
gards,
Bhawan
Bhawanpreet Lakha (10):
drm/amd/display: Add structs for Freesync Panel Replay
drm/amd/display: Add Functions to enable Freesync Panel Replay
drm/amd/display: Add Freesync Panel DM code
drm/amd/display: Read replay data from sink
drm/amd/display: Get replay info from VSDB
dr
Update infopackets for replay
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c | 4
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
Read DP_SINK_PR_PIXEL_DEVIATION_PER_LINE and
DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/dc/link/protocols/link_dp_capability.c | 10 ++
drivers/gpu/drm/amd/display/include/dpcd_defs.h| 2 ++
2 files changed, 12 insertions
- Add checks for Cursor update and dirty rects (sending updates to dmub)
- Add checks for dc_notify_vsync, and fbc and subvp
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 6 ++
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
Add various functions for replay, such as construct, destroy, enable
get_state, and copy_setting etc. These functions communicate with the
firmware to setup and enable panel replay
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +-
.../gpu/drm/amd
We need to make sure that the panel supports replay.
This info is inside the amd vsdb (vendor specific data block). Create a
function to parse the block and read the replay_mode bit.
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 44
Add Replay calls to clk_mgr updates (just like PSR)
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
- Setup replay config on device init.
- Enable replay if feature is enabled (prioritize replay over PSR, since
it can be enabled in more usecases)
- Add debug masks to enable replay on supported ASICs
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23
We need certain conditions for replay to be enabled, so create an
interface in DM to enable/disable replay.
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_replay.c | 176 ++
.../amd/display
Handle replay related hpd irqs
Signed-off-by: Bhawanpreet Lakha
---
.../dc/link/protocols/link_dp_irq_handler.c | 66 +++
1 file changed, 66 insertions(+)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
b/drivers/gpu/drm/amd/display/dc/link
On 2023-07-10 16:17, Alex Deucher wrote:
On Mon, Jul 10, 2023 at 3:27 PM Bhawanpreet Lakha
wrote:
This patch set introduces Freesync Panel Replay capability on DCN 3.1.4
and newer. Replay has been verified to be working with these patches (in
house)
These patches are enabling panel replay
signal_type to SIGNAL_TYPE_NONE unless it is eDP.
Signed-off-by: Sung Lee
Reviewed-by: Yongqiang Sun
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110
6.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
.../amd/display/dc/dce/dce_stream_encoder.c
translate into
p_state_change_support: false.
Signed-off-by: David Galiffi
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
.../gpu/drm/amd/display/dc
From: abdoulaye berthe
[Description]
When reading link, update the procedure as follows:
1-Set aux timeout to extended: 3.2ms
2-Start with reading lttpr caps
3-Determine if lttpr support should be enabled. Reset aux timeout to
400us if no repeater is found.
Signed-off-by: abdoulaye berthe
Revie
From: abdoulaye berthe
[Why]
LTTPR was introduced after DP1.2. Reading LTTPR registers 0xF
on some DP 1.2 display is causing an unexpected behavior.
[How]
Make sure that we don't read any lttpr registers on 1.2 displays.
Signed-off-by: abdoulaye berthe
Reviewed-by: Aric Cyr
---
drivers/g
.
[how]
Read back the enable state of DSC HW and report an error if duplicate
enable or disable was attempted.
Signed-off-by: Nikola Cornij
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 25 ---
1 file changed, 22
From: abdoulaye berthe
1-Read lttpr caps in 5-bytes
2-Parse caps
3-Validate caps and set lttpr_mode
4-Use hw default timeout when lttpr is disabled.
Signed-off-by: abdoulaye berthe
Reviewed-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 90 ++-
drivers/gpu
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7bf0241999c7..32eafff6b043 100644
since DCN2 and greater reports it on the OPP
instead of OTG, we patch it in after calling optc1_read_otg_states.
Ideally, this should be done in the DCN version specific function hooks.
It has been left as a TODO item.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Mikita Lipski
Acked-by: Bhawanpree
From: Jun Lei
[why]
Need it for some OEM I2C devices in Nv10
[how]
Link up code to parse OEM table and expose DC interface
to access the pins
Signed-off-by: Jun Lei
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/bios/bios_parser2.c| 63
not user visible since it is in
blank region.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 65 ++-
.../drm/amd/display/dc/dcn21
Summary Of Changes
*configure and init lttpr
*DSC sanity check
*Bandwidth optimization
*Some assert fixes
Anthony Koo (1):
drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC
SDP
Aric Cyr (2):
drm/amd/display: 3.2.57
drm/amd/display: 3.2.58
David Galiffi (2):
drm/am
-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +--
.../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ---
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
3 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 0416a17b0897..d931e5878b4c 100644
From: Yongqiang Sun
[Why]
DMCU isn't intiliazed properly by dmcub loading due to dmcub initialize
sequence.
[How]
Change dmcu init sequece to meet dmcub initilize.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/d
change for no
flip coming causing display count is 1 in SMU side.
Add optimize bandwidth after commit stream.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1 file changed, 4 insertions(+)
diff --git a
From: abdoulaye berthe
1-If at least one repeater is present in the link and we are in non
transparent mode, perform clock recovery then channel equalization
with all repeaters one by one before training DPRX.
2-Mark the end of LT with a repeater by setting training pattern 0
at the end of chann
From: abdoulaye berthe
[Description]
1-Grant extended timeout request. Done once after detection
2-Configure lttpr mode based on lttpr support before LT
3-Account for lttpr cap when determining max link settings
Signed-off-by: abdoulaye berthe
Reviewed-by: Aric Cyr
---
.../gpu/drm/amd/display
FW.
[How]
Add psp version mask 0x00FF00FF for checking version.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Acked-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: David Galiffi
[WHY]
V.Active dram clock change workaround need a small modification for DMLv2
to ensure that the dummy p-state check doesn't fail.
Signed-off-by: David Galiffi
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dml/
From: abdoulaye berthe
[Why]
The aux timeout value is not default before reading link cap.
Setting it to default when lttpr is not enabled causes some monitor
not to light up.
[How]
Read the aux engine timeout value before setting it to extended.
Set the aux engine timeout to its previous value
l_asic_id.h
* Expand DCN1 ifdef to include DCN21 code in the following files:
* clk_mgr/clk_mgr.c: dc_clk_mgr_create()
* core/dc_resources.c: dc_create_resource_pool()
* gpio/hw_factory.c: dal_hw_factory_init()
* gpio/hw_translate.c: dal_hw_translate_init()
Signed-off-by: Bhawanpreet Lak
Since dcn20 and dcn21 are under dcn1 it doesnt make sense to
have it named dcn1.
Change it to "dcn" to make it generic
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/Kconfig | 4 ++--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
drivers/g
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