_DISABLE_IPS2_DYNAMIC = 0x2000,
+
+ /**
+* @DC_FORCE_IPS_ENABLE: If set, force enable all IPS, all the time.
+*/
+ DC_FORCE_IPS_ENABLE = 0x4000,
};
enum amd_dpm_forced_level;
Reviewed-by: Aurabindo Pillai
--
Thanks & Regards,
Aurabindo Pillai
commit
drm/amd/display: Fix Synaptics Cascaded DSC Determination
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Aurabindo Pillai
--
Thanks & Regards,
Aurabindo Pillai
Summary:
* Revert some changes related to pixel encoding and clocks that cause
corruption
* IPS hang fix and FGCG enable by default for DCN35
* PSR-SU/Replay fixes
* Plane clip size change treated as medium update
* Fix for checking link alignment done during link tra
From: Zhikai Zhai
[WHY]
We Double-check link status if training successful,
but miss the lane align status.
[HOW]
Add the lane align status check
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Zhikai Zhai
---
.../gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
From: Sohaib Nadeem
[why]:
This reverts commit 5abbfa320b88da6034fd4121fa68c2b0e15e97ac.
The commit caused corruption when running some applications in fullscreen
Reviewed-by: Alvin Lee
Acked-by: Aurabindo Pillai
Signed-off-by: Sohaib Nadeem
---
drivers/gpu/drm/amd/display/dc/dml/dcn32
params in next program pipe.
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 7 ++-
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/hwss/dcn20
during create the
stream.
Reviewed-by: Aurabindo Pillai
Acked-by: Aurabindo Pillai
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display
mming when performing test pattern overrides.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dc.h | 12 +
.../display/dc/link/accessories/link_dp_cts.c | 27 +++---
.../hwss/link_hwss_dio_fixed_vs_pe_reti
From: Gabe Teeger
This reverts commit 3fda240dc2f6a4a9a3965b80cfb83d0ddfbf489c.
System hang observed, this commit is thought to be the
regression point.
Reviewed-by: Ovidiu Bunea
Acked-by: Aurabindo Pillai
Signed-off-by: Gabe Teeger
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35
: Aurabindo Pillai
Signed-off-by: Martin Tsai
---
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index ba1fec3016d5
From: Sohaib Nadeem
[why]:
issues fixed:
- comparison with wider integer type in loop condition which can cause
infinite loops
- pointer dereference before null check
Reviewed-by: Josip Pavic
Acked-by: Aurabindo Pillai
Signed-off-by: Sohaib Nadeem
---
.../gpu/drm/amd/display/dc/bios
From: Roman Li
[Why]
There is a potential memory access violation while
iterating through array of dcn35 clks.
[How]
Limit iteration per array size.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Roman Li
---
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
From: Charlene Liu
[why]
sw has most of the fgcg enabled which is the same as HW default.
but driver disabled some due to enable flag not initialized.
comparing HW state, we still need to enable dpp and dio.
Reviewed-by: Muhammad Ahmed
Acked-by: Aurabindo Pillai
Signed-off-by: Charlene Liu
From: George Shen
[Why/How]
A regression was identified with the change to add left edge pixel for
YCbCr422/420 + ODM combine cases.
This reverts commit 8d09500a33f6a0e0df9cf17822fe51520d0df002
Reviewed-by: Martin Leung
Acked-by: Aurabindo Pillai
Signed-off-by: George Shen
---
drivers/gpu
-by: Charlene Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 83 +++--
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 6 +-
.../gpu/drm/amd/display/dmub/inc
From: Charlene Liu
[why]
allow psr-su/replay for z8
Reviewed-by: Muhammad Ahmed
Reviewed-by: Sung joon Kim
Acked-by: Aurabindo Pillai
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 12 ++--
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
.
* HDMI compliance test fixes and other improvements
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Nicholas Kazlauskas
[Why]
New worst-case measurement observed at 1897us.
[How]
Increase to 2000us to cover the new worst case + margin.
Reviewed-by: Ovidiu Bunea
Acked-by: Aurabindo Pillai
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/resource/dcn35
Add new firmware header definitions reqiured for DCN401
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/include/atomfirmware.h | 33 ++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include
Idle optimizations were disabled due to some bugs which are now fixed in
DMCUB and PM firwmare. Enable these the optimizations back.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c| 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers
From: Likun Gao
Add support to init TA firmware for psp v14.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
index cc0248efa6b6..4d33c95
Add the necessary register definitions to enable DCC on DCN4x
Signed-off-by: Aurabindo Pillai
---
.../include/asic_reg/dcn/dcn_4_1_0_sh_mask.h | 110 ++
1 file changed, 110 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
b/drivers/gpu
Add registers and entry points to enable DCC on DCN4x
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 11 +
drivers/gpu/drm/amd/display/dc/dc.h | 4 +
.../drm/amd/display/dc/dml2
Add some register offsets that are required for Display DCC on DCN401
Fixes: 000342e3a22 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis
Signed-off-by: Aurabindo Pillai
---
.../include/asic_reg/dcn/dcn_4_1_0_offset.h| 18 ++
1 file c
] ? dm_update_plane_state.constprop.0+0x4e3/0x6b0 [amdgpu]
[ 181.850840] amdgpu_dm_atomic_check+0xdfe/0x1760 [amdgpu]
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers
state,
curr_pipe->plane_state);
+ if (!phantom_plane)
+ return;
}
memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
--
--
Thanks & Regards,
Aurabindo Pillai
Reviewed-by: Aurabindo Pillai
On 6/26/24 2:31 PM, Marek Olšák wrote:
Checking SWIZZLE_MODE has undefined behavior on gfx12.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers
Reviewed-by: Aurabindo Pillai
On 6/26/24 2:31 PM, Marek Olšák wrote:
All this code has undefined behavior on GFX12 and shouldn't be executed.
Signed-off-by: Marek Olšák
---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 47 ++-
1 file changed, 25 insertions(+
ne_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
rotation, plane_size,
tiling_info, dcc,
Reviewed-by: Aurabindo Pillai
--
Thanks & Regards,
Aurabindo Pillai
Reviewed-by: Aurabindo Pillai
On 6/26/24 2:31 PM, Marek Olšák wrote:
Signed-off-by: Marek Olšák
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm
Reviewed-by: Aurabindo Pillai
On 6/26/24 2:31 PM, Marek Olšák wrote:
There were multiple bugs, like checking SWIZZLE_MODE before checking
GFX12_SWIZZLE_MODE, which has undefined behavior.
The function had no effect before (it always returned -EINVAL).
Signed-off-by: Marek Olšák
Reviewed-by: Aurabindo Pillai
On 6/26/24 2:31 PM, Marek Olšák wrote:
They were added accidentally.
Signed-off-by: Marek Olšák
---
include/uapi/drm/drm_fourcc.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index
] ? dm_update_plane_state.constprop.0+0x4e3/0x6b0 [amdgpu]
[ 181.850840] amdgpu_dm_atomic_check+0xdfe/0x1760 [amdgpu]
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd
To enable mesa to use display dcc, DM should expose them in the
supported modifiers. Add the best (most efficient) modifiers first.
Signed-off-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 31 +++
1 file changed, 25 insertions(+), 6 deletions(-)
diff
On 7/10/24 10:49 AM, Marek Olšák wrote:
This will enable display DCC for Wayland because Mesa already exposes
modifiers with DCC. Has it been tested?
Yes, its working for most resolutions. Investigating issue with certain
modes.
Marek
--
Thanks & Regards,
Aurabindo Pillai
On 7/10/24 4:12 PM, Marek Olšák wrote:
Can you also increase KMS_DRIVER_MINOR with a proper comment in
amdgpu_drv.c, which will be used by Mesa to tell whether display DCC
is supported on gfx12?
Sure, will do.
--
Thanks & Regards,
Aurabindo Pillai
Increase the KMS minor version to indicate GFX12 DCC support since this
contains a major change in how DCC is managed across IPs like GFX, DCN
etc. This will be used mainly by userspace like Mesa to figure out
DCC support on GFX12 hardware.
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm
Fixes the warning:
Function parameter or struct member 'bb_from_dmub' not described in
'amdgpu_display_manager'
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a
phen Rothwell
this patch is:
Reviewed-by: Aurabindo Pillai
--
Thanks & Regards,
Aurabindo Pillai
Reviewed-by: Aurabindo Pillai
On 7/15/24 4:57 PM, roman...@amd.com wrote:
From: Roman Li
[Why]
htmldocs warning:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h: warning:
Function parameter or struct member 'idle_workqueue' not described in
'amdgpu_display_manager'
9d7
drm/amd/display: fix documentation warnings for mpc.h
--
Thanks & Regards,
Aurabindo Pillai
Wheeler
Alex Hung (2):
drm/amd/display: Add MST debug message when link detection fails
drm/amd/display: Check link_res->hpo_dp_link_enc before using it
Aric Cyr (1):
drm/amd/display: 3.2.293
Aurabindo Pillai (3):
drm/amd/display: rename dcn3/dcn4 to more sound terms
drm/amd/display: ren
From: Dillon Varone
[WHY&HOW]
Hardmax message will be retired for dcn4, so this removes it.
Reviewed-by: Alvin Lee
Signed-off-by: Aurabindo Pillai
Signed-off-by: Dillon Varone
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 44 ++-
drivers/gpu/drm/amd/display/dc/
From: Sung Joon Kim
[why & how]
Need to make sure plane_state is initialized
before accessing its members.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Xi (Alex) Liu
Signed-off-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm
From: Hansen Dsouza
[why & how]
Add private data types for better RCG control
Reviewed-by: Chris Park
Reviewed-by: Yihan Zhu
Signed-off-by: Aurabindo Pillai
Signed-off-by: Hansen Dsouza
---
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 81 +++
1 file changed
From: Revalla Hari Krishna
[Why]
To refactor HPO files
[How]
Moved hpo related files to specific hpo folder and
update Makefiles.
Reviewed-by: Martin Leung
Signed-off-by: Aurabindo Pillai
Signed-off-by: Revalla Hari Krishna
---
drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 2
the
ASSERT if the significance is equal to zero to avoid unnecessary noise.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Chaitanya Dhere
Signed-off-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../dml2/dml21/src/dml2_standalone_libraries
From: Hansen Dsouza
[why & how]
Add standard RCG helpers based on DCCG spec
Reviewed-by: Daniel Miess
Reviewed-by: Muhammad Ahmed
Signed-off-by: Aurabindo Pillai
Signed-off-by: Hansen Dsouza
---
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 307 ++
1 file changed,
force EASF coefficients programming
Reviewed-by: Alvin Lee
Signed-off-by: Aurabindo Pillai
Signed-off-by: Samson Tam
---
.../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 28 +--
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp
From: Ryan Seto
[Why]
Visual confirm was incorrect on dual monitor SubVP setup
[How]
Adjusted p_state assignment for dual monitor SubVP setup
Signed-off-by: Ryan Seto
Reviewed-by: Chaitanya Dhere
Signed-off-by: Aurabindo Pillai
---
.../dc/dml2/dml21/dml21_translation_helper.c | 13
From: Austin Zheng
[Why]
Even if the mode is not supported dml2_check_mode_supported() would still
return true.
This causes an unsupported mode to be programmed.
[How]
Check if the mode is supported or not and return the proper result.
Reviewed-by: Chaitanya Dhere
Signed-off-by: Aurabindo
From: Hansen Dsouza
[why & how]
Add source select helpers based on DCCG spec
Reviewed-by: Daniel Miess
Signed-off-by: Aurabindo Pillai
Signed-off-by: Hansen Dsouza
---
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 324 ++
1 file changed, 324 insertions(+)
diff --g
Use more accurate names to refer to the asic architecture.
dcn3 in DML actually refers to DCN32 and DCN321, so rename it to dcn32x
dcn4 refers to any DCN4x soc., and hence rename dcn4 to dcn4x
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
Signed-off-by: Aurabindo Pillai
To distinguish between different soc with same DCN IP, use variants
starting with alphabets
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c| 2 +-
.../amd/display/dc/dml2/dml21
From: Ilya Bakoulin
[Why/How]
Need to identify which fast updates will update more than just the
address.
Reviewed-by: Alvin Lee
Signed-off-by: Aurabindo Pillai
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 25 +++-
drivers/gpu/drm/amd
From: Gabe Teeger
[what & why]
System hang after s4 regression points to code change here.
Removing possible NULL dereference.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Aurabindo Pillai
Signed-off-by: Gabe Te
DTBCLK and causes
hang.
[how]
For DP2.0 MST hubs, only treat 1st remote sink as an encoder
only when there are multiple displays connected.
Reviewed-by: Michael Strauss
Signed-off-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
---
.../amd/display/dc/dml2/dml2_internal_types.h | 1 +
.../display
From: Alex Hung
[WHY & HOW]
dc_link_detect returns a boolean value which can be used to print debug
messages when it fails.
This fixes 1 CHECKED_RETURN issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
Signed-off-by: Alex Hung
---
drivers/gpu/drm
From: Alex Hung
[WHAT & HOW]
Functions dp_enable_link_phy and dp_disable_link_phy can pass link_res
without initializing hpo_dp_link_enc and it is necessary to check for
null before dereferencing.
This fixes 1 FORWARD_NULL issue reported by Coverity.
Fixes: abdcd93214 ("drm/amd/display: Check l
From: Rodrigo Siqueira
Remove some old comments from DCN32/321.
Signed-off-by: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 4 ++--
2 files changed, 4 insertions
From: Dillon Varone
The disable fams2 operation was reworked, but some of the old code
remained. This commit removes the disable_fams2_drr from the
dml2_stream_parameters.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
Signed-off-by: Aurabindo Pillai
---
.../amd/display/dc/dml2
HWSS.
- update_plane_addr should only be public, as it's used outside HWSS.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Joshua Aberback
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 1 -
.../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq
dc/{dcn401,dcn303} are unused since the files in it got moved under their
respective new components location. Hence they are no longer necessary
Fixes: fb17441f8ce4 ("drm/amd/display: Refactor DCN3X into component folder")
Signed-off-by: Aurabindo Pillai
Reviewed-by: Leo Li
---
drive
From: Aric Cyr
Signed-off-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 272ae1bdc57f..4077c1ddb9c1 100644
Summary:
* Changes across DSC, MST, DMCUB, Panel Replay and misc fixes.
* Fixes to cursor programming sequence
* Add some missing register defs
* Formatting/Sytle fixes
==
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.214.0
Aric Cyr (1):
drm/am
From: Rodrigo Siqueira
This commit add some missing debug registers for DPCS and RDPC debug.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 5 +++-
.../display/dc/dcn31/dcn31_dio_link_encoder.h | 2
From: Rodrigo Siqueira
DCN3.0 supports some specific DWB debug registers that are not exposed
yet. This commit just adds the missing registers.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h | 14
From: Rodrigo Siqueira
Add TMDS balancer control to the list of available encoder registers for
DCN 30.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h | 3 ++-
1 file changed, 2
From: Rodrigo Siqueira
This commit add some missing HDMI control registers to DCN3x.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 3 +++
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
From: Dmytro Laktyushkin
Headless dp 2.0 will take longer to update.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Rodrigo Siqueira
This commit removes some unnecessary code and makes the required
adjustments to replace other parts of the code with a short option.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dce
From: George Shen
Theoretically rare corner case where ceil(Y) results in rounding up to
an integer. If this happens, the 1 should be carried over to the X
value.
CC: sta...@vger.kernel.org
Reviewed-by: Rodrigo Siqueira
Signed-off-by: George Shen
Tested-by: Daniel Wheeler
---
.../drm/amd/dis
From: Rodrigo Siqueira
This commit reorganizes the order in which some control registers are
presented to make it easier to identify the operations based on the
hardware doc.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc
From: Rodrigo Siqueira
This commit address some small code style issues in DC.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c| 3 +--
drivers/gpu/drm/amd/display/dc/dm_helpers.h
From: Rodrigo Siqueira
Add some missing HDCP registers to be used in DCN35.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../amd/display/dc/dcn35/dcn35_dio_link_encoder.h| 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff
From: Rodrigo Siqueira
In the DCN20 resource initialization, ensure that DMCUB support starts
configured as true.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 1 +
1 file changed, 1
From: Rodrigo Siqueira
This commit adds, updates, and removes some of the comments used in the
DC code.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h| 2 +-
.../gpu/drm/amd/display/dc/dpp/dcn201
From: Rodrigo Siqueira
This commit add some DPCX IRQ types.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/irq_types.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc
From: Rodrigo Siqueira
Drop unnecessary semicolon that can create a problem of double semicolon
in some compilers.
Reviewed-by: Martin Leung
Acked-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h | 3
From: Dennis Chan
When PHY power off, the DP_SEC_CNTL cannot be configured and cause
disable Adaptive sync SDP failed. Regarding the issue, the driver will
disabled AS-SDP in replay state machine.
Reviewed-by: ChunTao Tso
Acked-by: Aurabindo Pillai
Signed-off-by: Dennis Chan
Tested-by
eck in dc_resource.c/resource_log_pipe_topology_update.
CC: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Natanel Roizenman
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers
wed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
Signed-off-by: Swapnil Patel
Tested-by: Daniel Wheeler
---
.../drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
b/drive
From: Sung Joon Kim
[why & how]
Need to update the function pointers that
perform the power up and down sequence
to reuse the modified sequence as a requirement.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
dri
: Aurabindo Pillai
Signed-off-by: Sung-huai Wang
Tested-by: Daniel Wheeler
---
.../dc/link/protocols/link_dp_irq_handler.c | 25 ---
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
b/drivers/gpu
From: Michael Strauss
[WHY]
Avoid race condition which puts LTTPR into bad state during UHBR LT.
[HOW]
Delay 30ms between starting UHBR TPS1 PHY output and sending TPS1 via DPCD.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Michael Strauss
Tested-by: Daniel Wheeler
be skipped when clearing the payload allocation table.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: George Shen
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/
w BIOS
version 2.3.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Gabe Teeger
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/d
flicker.
- Generalized increase/reduce dependent functions to reduce code clutter
and allow for easier use.
- Added a debug option to enable the feature. Disabled by default.
Co-authored-by: Ethan Bitnun
Reviewed-by: Dillon Varone
Acked-by: Aurabindo Pillai
Signed-off-by: Ethan Bitnun
From: Nicholas Kazlauskas
[Why]
It's possible that the write hasn't fully completed by the time we
send (and flush) a command to DMCUB to notify idle to request IPS2
exit.
[How]
Perform a readback of the volatile structure into dc_dmub_srv state.
Reviewed-by: Charlene Liu
Acked-by:
tor->sink check to find pipe_ctx.
CC: sta...@vger.kernel.org
Reviewed-by: Aurabindo Pillai
Signed-off-by: Hersen Wu
Tested-by: Daniel Wheeler
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 48 ++-
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/g
, this causes bw allocation failure
when allocation greater than estimated bw.
[How]
Do zero alloc to make the CM to release preallocation and
update estimated BW correctly for all DPIAs per host router.
Reviewed-by: PeiChen Huang
Acked-by: Aurabindo Pillai
Signed-off-by: Meenakshikumar
From: Ilya Bakoulin
Not every ASIC implements dp_set_dsc_config. Add condition to prevent
calls to unimplemented function.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Ilya Bakoulin
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 16
-by: Chaitanya Dhere
Acked-by: Aurabindo Pillai
Signed-off-by: Joshua Aberback
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
b/drivers
ommits.
Reviewed-by: Agustin Gutierrez
Acked-by: Aurabindo Pillai
Signed-off-by: Harry Wentland
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 87
s
first to ensure hubp has the right attributes to be programmed.
Reviewed-by: Agustin Gutierrez
Acked-by: Aurabindo Pillai
Signed-off-by: Harry Wentland
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_h
From: Sung Joon Kim
[why & how]
The recout x offset was incorrect which led to
wrong viewport calculation. For stereo
side-by-side case, the slice index should be
0 for both split pipes.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Da
From: Cruise
[Why]
Error correction was enabled in a monitor which doesn't support.
[How]
Disable error correction if it's not supported
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Cruise
Tested-by: Daniel Wheeler
---
.../display/dc/link/protocols/lin
From: Sung Joon Kim
[why & how]
There are potential issues with Z8 and IPS
that need to be addressed and need to add
in missing function pointers.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
drivers/gpu/drm
mode set.
Reviewed-by: Jun Lei
Acked-by: Aurabindo Pillai
Signed-off-by: yi-lchen
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++
.../drm/amd/display/dc/dcn314/dcn314_dccg.c | 12 ++---
.../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 13 +++---
.../
From: Rodrigo Siqueira
The string dp_hdmi_dongle_signature_str already uses u8 but the string
dp_hdmi_dongle_signature_str does not. Just replace uint8_t with u8 for
dp_hdmi_dongle_signature_str.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
Tested-by
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