.org/patch/msgid/20210524131852.263883-2-max...@cerno.tech
Signed-off-by: Anson Jacob
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index df65e0b6449b..aab1b36ceb3c 100
- Remove invalid assert for ODM + MPC case
Anson Jacob (1):
drm/amd/display: use GFP_ATOMIC in amdgpu_dm_irq_schedule_work
Anthony Koo (2):
drm/amd/display: [FW Promotion] Release 0.0.78
drm/amd/display: 3.2.148
Ashley Thomas (1):
drm/amd/display: Add AUX I2C tracing.
Eric Bernstein (1
From: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Anson Jacob
Signed-off-by: Eric Bernstein
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30
From: Roy Chan
Acked-by: Anson Jacob
Signed-off-by: Roy Chan
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index
From: Roy Chan
[How]
the programming sequeune was for old asic.
the correct programming sequeunce should be similar to the one
used in mpc. the fix is copied from the mpc programming sequeunce.
Acked-by: Anson Jacob
Signed-off-by: Roy Chan
---
.../drm/amd/display/dc/dcn30/dcn30_dwb_cm.c
From: Roy Chan
Acked-by: Anson Jacob
Signed-off-by: Roy Chan
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 62
1 file changed, 41 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index
From: Wenjing Liu
[why]
DM needs to be notified when hdcp module has completed
authentication attempt.
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 5 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 8 ++
.../display/modules/hdcp
From: Roy Chan
[Why]
If the plane has been removed, the writeback disablement logic
doesn't run
[How]
fix the logic order
Acked-by: Anson Jacob
Signed-off-by: Roy Chan
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 14 --
drivers/gpu/drm/amd/display/dc/
for ODM + MPC case
Reviewed-by: Wyatt Wood
Acked-by: Anson Jacob
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 62c222d0402f
From: Roy Chan
Acked-by: Anson Jacob
Signed-off-by: Roy Chan
---
.../gpu/drm/amd/display/dc/core/dc_stream.c | 106 +++---
1 file changed, 65 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core
From: Ashley Thomas
[Why]
Developers can find it useful if the driver can produce
AUX traces without special equipment.
[How]
Add AUX tracing.
Reviewed-by: Zhan Liu
Acked-by: Anson Jacob
Signed-off-by: Ashley Thomas
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 192
From: Anthony Koo
Acked-by: Anson Jacob
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Nicholas Kazlauskas
[Why]
If we're backdoor loading the DMCUB performs more work than just
the PHY reset so we can end up resetting before the cleanup has fully
finished.
[How]
Increase timeout, add udelay between spins to guarantee a minimum.
Acked-by: Anson Jacob
Signed-o
Jayamohanan Pillai
Acked-by: Anson Jacob
Signed-off-by: Anson Jacob
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
b/drivers/gpu/drm/
1002.
[How]
Move the GPINT clear outside of the reset loop and do it unconditionally
after the DMCUB has been properly reset.
Reviewed-by: Roy Chan
Reviewed-by: Eric Yang
Acked-by: Anson Jacob
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 8
Assert only when FPU is not enabled.
Fixes: e549f77c1965 ("drm/amd/display: Add DC_FP helper to check FPU state")
Signed-off-by: Anson Jacob
Cc: Christian König
Cc: Hersen Wu
Cc: Harry Wentland
Cc: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 2 +-
1 file
Add dummy function when CONFIG_HSA_AMD is not enabled.
Fixes: 433d2448d57c ("drm/amdkfd: separate kfd_iommu_resume from kfd_resume")
Signed-off-by: Anson Jacob
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/
Remove unused variable 'size'.
Signed-off-by: Anson Jacob
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 9274f32c3661..bc1297dcdf97 100644
--- a/drive
Tested on nixeus 4k144hz DSC capable display on
RX5700XT (NAVI10 0x1002:0x731F 0x1DA2:0xE410 0xC1)
on ubuntu 20.04. Display lightsup at 4k144hz with DSC engine on.
Tested-by: Anson Jacob
On 2021-09-07 10:32 a.m., Qingqing Zhuo wrote:
As part of the FPU isolation work documented in
https
Hi Harry,
This patch fixes the following CID's. Thanks.
Addresses-Coverity-ID: 1424031: ("Big parameter passed by value")
Addresses-Coverity-ID: 1423970: ("Big parameter passed by value")
Addresses-Coverity-ID: 1423941: ("Big parameter passed by value")
Addresses-Coverity-ID: 1451742: ("Big para
Hi Harry,
This patch fixes the following CID's. Thanks.
Addresses-Coverity-ID: 1423868: ("Big parameter passed by value")
Addresses-Coverity-ID: 1423870: ("Big parameter passed by value")
-- Anson
Hi Harry,
This patch fixes the following CID's. Thanks.
Addresses-Coverity-ID: 1424031: ("Big parameter passed by value")
Addresses-Coverity-ID: 1424055: ("Big parameter passed by value")
Addresses-Coverity-ID: 1424072: ("Big parameter passed by value")
Addresses-Coverity-ID: 1423779: ("Big para
This DC patchset brings improvements in multiple areas. In summary, we
have:
- Fixes to backlight, LUT, PPS, MST
- Use correct vpg for 128b/132b encoding
- Improved logging for VCP
- Replace referral of dal with dc
Anthony Koo (2):
drm/amd/display: [FW Promotion] Release 0.0.85
From: Anthony Koo
Acked-by: Anson Jacob
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Wenjing Liu
[why]
128b/132b uses the vpg instance assigned to hpo dp stream encoder.
The current vpg used is assigned to dio stream encoder.
This is incorrect and cause display black screen because the
actual vpg is powered off.
Reviewed-by: Michael Strauss
Acked-by: Anson Jacob
Signed
From: Michael Strauss
[WHY]
AFMT is unused for DP audio, so powering it on for DP is unnecessary.
[HOW]
APG block should be powered down instead, however HW defaults to shutdown
state when not enabled so no further work is required.
Reviewed-by: Wenjing Liu
Acked-by: Anson Jacob
Signed-off
From: David Galiffi
[Why]
Requested feature to assist with Thermal, Acoustic, Power, and
Performance tuning.
[How]
Add a debug field that will override calculated minimum DRAM clock,
if the debug value is larger than the calculate value.
Reviewed-by: Alvin Lee
Acked-by: Anson Jacob
Signed
ed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
Signed-off-by: Eric Yang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 54 +++
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 21
drivers/gpu/drm/amd/display/dc/i
From: Wenjing Liu
[why]
To support per lane lane setting adjustment, we need to change cur_lane_setting
to an array one for each lane as the first step.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8
From: Wenjing Liu
[why]
Unify the code which handles the conversion between hw lane setting
and dpcd lane setting.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 113 ++
.../gpu/drm/amd/display/dc/inc
From: Wenjing Liu
[why]
Decouple lane settings decision logic all to its own function.
The function takes in lane adjust array and link training settings
and decide what hw lane setting and dpcd lane setting should be used.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
From: Wenjing Liu
[why]
This is one of the major steps to decouple hw lane settings
from dpcd lane settings.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++--
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 38
individually.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 154 +++---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 5 -
.../amd/display/include/link_service_types.h | 19 ++-
3 files changed, 70 insertions
From: Wenjing Liu
[why]
option 1: disallow different lanes to have different lane settings
option 2: dpcd lane settings will always use the same hw lane settings
even if it doesn't match requested lane adjust
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
..
the stream for which the availability
check is being conducted. If the link is shared, then the link
encoder should be shared too and will be deemed available.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Jimmy Kizito
---
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 23
From: Meenakshikumar Somasundaram
[Why]
Link encoder in the link could be null for certain links.
[How]
If link encoder in the link is null then get the link encoder
from the stream.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Meenakshikumar Somasundaram
---
drivers/gpu/drm
From: Oliver Logush
Reviewed-by: Charlene Liu
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Oliver Logush
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 6 --
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
Acked-by: Anson Jacob
Signed-off-by: Ilya
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c| 5 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 9 ++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20
From: Anthony Koo
Acked-by: Anson Jacob
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Aric Cyr
This version brings along following fixes:
- Fixes to backlight, LUT, PPS, MST
- Use correct vpg for 128b/132b encoding
- Improved logging for VCP
- Replace referral of dal with dc
Acked-by: Anson Jacob
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1
Vupdate.
[HOW]
Re-enable mem low power for CM block
Force optimization on next flip and disable LUT memory during optimization
sequence if LUT select field is then set to bypass
Reviewed-by: Eric Yang
Acked-by: Anson Jacob
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc.c
From: Qingqing Zhuo
[Why]
DC should be used in place of DAL in
upstream.
[How]
Replace dal with dc in function names.
Reviewed-by: Rodrigo Siqueira
Acked-by: Anson Jacob
Signed-off-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +-
drivers/gpu/drm
From: Josip Pavic
[Why]
Stack variable params.backlight_ramping_override is uninitialized, so it
contains junk data
[How]
Initialize the variable to false
Reviewed-by: Roman Li
Acked-by: Anson Jacob
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1
-by: Jimmy Kizito
Acked-by: Anson Jacob
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 43 ---
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core
From: George Shen
[Why/How]
Theoretically rare corner case where ceil(Y) results in rounding
up to an integer. If this happens, the 1 should be carried over to
the X value.
Reviewed-by: Wenjing Liu
Acked-by: Anson Jacob
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/dcn10
From: Charlene Liu
[why]
pci deviceid not passed to dal dc, without proper break,
dcn2.x falls into dcn3.x code path
[how]
pass in pci deviceid, and break once dal_version initialized.
Reviewed-by: Zhan Liu
Acked-by: Anson Jacob
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display
and format output to be human readable.
Reviewed-by: Wenjing Liu
Acked-by: Anson Jacob
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 49 ++-
1 file changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core
Commit 4d706ed6825f ("drm/amdkfd: clean up parameters in kgd2kfd_probe")
updated paremeters for kgd2kfd_probe. Update the dummy function as well
when CONFIG_HSA_AMD is not enabled.
Fixes: 4d706ed6825f ("drm/amdkfd: clean up parameters in kgd2kfd_probe")
Signed-off-by: Anson
/display: Wait for ACK for INBOX0 HW Lock
Angus Wang (1):
drm/amd/display: Fix RGB MPO underflow with multiple displays
Anson Jacob (1):
drm/amd/display: Add comment where CONFIG_DRM_AMD_DC_DCN macro ends
Aric Cyr (1):
drm/amd/display: 3.2.161
Charlene Liu (3):
drm/amd/display: remove
Alvin Lee
Reviewed-by: Wesley Chalmers
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 51 +++
drivers/gpu/drm/amd/display/dc/dc_link.h | 4 ++
.../display/dc/dce110/dce110_hw
Trivial patch which adds a comment for macro
endif's in amdgpu_dm.c
Reviewed-by: Ariel Bernstein
Reviewed-by: Harry Wentland
Acked-by: Anson Jacob
Signed-off-by: Anson Jacob
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
drivers/gpu/drm/amd/display/dc/core
ed-by: Anson Jacob
Signed-off-by: Mikita Lipski
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 2 +-
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/dr
Acked-by: Anson Jacob
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index
From: Charlene Liu
[why]
matching the dmcub_support with all other dcn version.
Reviewed-by: Sung joon Kim
Reviewed-by: Martin Leung
Acked-by: Anson Jacob
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 --
1 file changed, 2 deletions(-)
diff
w]
To maintain compatibility with already released firmware where this
occurs we need to try every meta offset from 0..15 inclusive.
Extract out the meta info checker into a helper function that's called
for each of these offsets and exit early when we've found it.
Reviewed-by: Eric Yang
From: Charlene Liu
[why]
reduce az indirect register dump. need add az
clock_gating control field used in some project.
[how]
conditional output indrect register in the log.
add clock_gating feild
Reviewed-by: Sung joon Kim
Acked-by: Anson Jacob
Signed-off-by: Charlene Liu
---
drivers/gpu
From: Dmytro Laktyushkin
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 8
.../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h | 7 +++
2 files changed, 11 insertions
idle. Added a two step call to
dc_update_planes_and_stream, first time with pipe split
disabled and the second time with pipe split enabled, which
fixed the underflow issue
Change-Id: I2d6fcc146242a30849096f08c52afa13bf4f9225
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
Signed-off-by: Angus Wang
From: "Huang, ChiaWen"
[Why & How]
According to eDP spec, DPCD 1.3 is only for eDP DPCD v1.4
In dpcd_set_link_settings function, the driver is just above v1.3
Reviewed-by: Wenjing Liu
Acked-by: Anson Jacob
Signed-off-by: ChiawenHuang
---
drivers/gpu/drm/amd/display/dc/core/dc
the unassign loop does the work properly,
the loop should base on the current state to clean up the assignment.
Also, the unassignment should better clean up the values in the
assignement slots as well.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Roy Chan
---
.../drm/amd/display
ble is static at creation - we don't dynamically add or remove links,
just streams.
Fixes: 00be4268d32c ("drm/amd/display: Support for DMUB HPD interrupt handling")
Reviewed-by: Jude Shih
Acked-by: Anson Jacob
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amd
From: Chris Park
[Why]
Coverity discovers holes in logic that
needs to be addressed for improved
code integrity.
[How]
Address issues found by coverity without
changing the actual logic.
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display
it indicates if we want
to reference the stream pointer or not.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core
From: Charlene Liu
Reviewed-by: Sung joon Kim
Acked-by: Anson Jacob
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc
From: Robin Chen
[Why]
Some panels require to use TPS3 pattern to wake up link in PSR mode.
[How]
To add TPS3 selection information in PSR settings command and pass to
DMUB FW.
Reviewed-by: Anthony Koo
Acked-by: Anson Jacob
Signed-off-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dce
HPD handler to also handle HPD IRQ (RX) since the logic is
the same.
Fixes: 00be4268d32c ("drm/amd/display: Support for DMUB HPD interrupt handling")
Reviewed-by: Wayne Lin
Reviewed-by: Jude Shih
Acked-by: Anson Jacob
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display
.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 37 +++--
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 2 +
.../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 3 ++
drivers/gpu/drm/amd/display/dmub
ked-by: Anson Jacob
Signed-off-by: Meenakshikumar Somasundaram
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +++---
.../drm/amd/display/dc/core/dc_link_dpia.c| 20 +--
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
3 files changed, 14 insertions(+), 13 del
From: Aric Cyr
This version brings along following fixes:
- Improvements to INBOX0 HW Lock
- Add support for sending TPS3 pattern
- Fix Coverity Issues
- Fixes for DMUB
- Fix RGB MPO underflow with multiple displays
- WS fixes and code restructure
Acked-by: Anson Jacob
Signed-off-by: Aric Cyr
-by: Anson Jacob
Signed-off-by: Jimmy Kizito
---
.../gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index
assignments are
invalid.
[How]
Initialise encoder assignment variables when creating new dc_state
resource.
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +
drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
Removing code that is not used at the moment.
Signed-off-by: Anson Jacob
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 37 ---
1 file changed, 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
This patchset brings along following features/fixes:
- LTTPR improvements
- Disable MALL when SMU not present
- Fix bug in HW that causes P-State to hang when DPG is enabled in
certain conditions
- Update code path for enabling DPG
- Update display endpoint control path
Siqueira
Reviewed-by: Harry Wentland
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 19 +++
3 files changed, 34 insertions(+)
diff
From: Wesley Chalmers
[WHY]
Some platforms will have LTTPR capabilities forced on by VBIOS flags;
the functions added here will access those flags.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
.../drm/amd/display/dc/bios/bios_parser2.c| 139
From: Stylon Wang
[Why]
ASSR enabling only considers capability declared in DPCD.
We also need to check whether the connector is internal.
[How]
ASSR enabling need to check both DPCD capability and internal display
flag.
Signed-off-by: Stylon Wang
Reviewed-by: Harry Wentland
Acked-by: Anson
From: Wenjing Liu
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 6 +++---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c| 4 ++--
drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 10
From: Qingqing Zhuo
[Why]
Color depth data is not parsed during test requests.
[How]
Update display color depth according to color depth
request from the test equipment.
Signed-off-by: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/dc/core
From: Wenjing Liu
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 6 +++
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 4 +-
.../display/modules/hdcp/hdcp1_execution.c| 37 +++
.../display
From: "Leo (Hanghong) Ma"
[Why]
Static analysis on linux-next has found a potential null pointer
dereference;
[How]
Refactor the function, add ASSERT and remove the unnecessary check.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Acked-by: Anson Jacob
---
.../g
From: Vladimir Stempen
[why]
Word "remainder" was misspelled as "reminder" in
reduceSizeAndFraction method variable.
[how]
Fix the spelling.
Signed-off-by: Vladimir Stempen
Reviewed-by: Alexander Deucher
Reviewed-by: Bindu R
Acked-by: Anson Jacob
---
.../gpu/drm/
From: Wesley Chalmers
[WHY]
The logic to toggle LTTPR transparent/non-transparent requires 2 flags
provided by BIOS
[HOW]
Repurpose the interface to get dce caps so both LTTPR querying functions
can use them.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
From: Krunoslav Kovac
[Why&How]
Renaming structure to better indicate its meaning.
Signed-off-by: Krunoslav Kovac
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
Acked-by: Anthony Koo
---
drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 +++---
drivers/gpu/drm/amd/display/mod
3200 us and per-hop
link training is done
[HOW]
Use an enum instead of a bool to track LTTPR state; modify comparisons
accordingly.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 33 +--
.../drm/amd
From: Wesley Chalmers
[WHY]
Some systems can enable LTTPR through bits in BIOS, while other systems
can be configured at boot to enable LTTPR. Some configs enable
Non-Transparent mode, while others enable Transparent mode.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson
ed-by: Aurabindo Jayamohanan Pillai
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
From: Wesley Chalmers
[WHY]
We want to make enabling test pattern a part of the
stream update code path. This change is the first step
towards that goal.
Signed-off-by: Wesley Chalmers
Reviewed-by: Aric Cyr
Reviewed-by: Tony Cheng
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc
tracking variables.
- Execute link encoder assignment algorithm before enabling link and
release link encoders from links once they are disabled.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/Makefile | 5 +-
drivers/gpu/drm/amd
get updated.
When DPG is enabled, update the ttu_regs.min_ttu_vblank field of each
pipe in the stream's topology to the maximum value (0xff).
Signed-off-by: Wesley Chalmers
Reviewed-by: Tony Cheng
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc.c
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 15 ++-
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 99 +++
.../drm/amd/display/dc/core/dc_link_hwss.c| 22 -
.../gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 18
4 files changed, 146
From: Qingqing Zhuo
[Why&How]
Add log for easier debug purposes.
Signed-off-by: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/displa
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd
issues
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 55f3c76823d8..8b725347e2ed
From: Chris Park
[Why]
Bring-up purpose code to disable DMUB calling into
SMU and timeout for MALL when SMU is not present.
[How]
Disable MALL when SMU is not present.
Signed-off-by: Chris Park
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/dc/clk_mgr
1. Remove duplicate OTG_PIXEL_RATE_CNTL from dccg_registers
2. Fixes: 18827ee0cc28 ("drm/amd/display: Refactor visual confirm")
Signed-off-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 -
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 3 +--
2 files
From: Po-Ting Chen
[Why]
To change the swizzle visual confirm reference pipe from top pipe to
bottom pipe due to bottom pipe information would be more important
for multiple overlay case.
Signed-off-by: Po-Ting Chen
Reviewed-by: Anthony Koo
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd
From: Aric Cyr
This version brings along following fixed:
- LTTPR improvements
- Backlight improvements
- eDP hotplug detection
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1
This DC patchset brings improvements in multiple areas. In summary, we have:
* LTTPR improvements
* Backlight improvements
* eDP hotplug detection
*** BLURB HERE ***
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.70
Aric Cyr (1):
drm/amd/display: 3.2.140
Ashley Thomas (1):
d
LTTPRs detected and
Non-Transparent is
requested.
Write Transparent in all other cases.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers
From: Wenjing Liu
[why]
Move mst start top mgr in dc_link_detect layer.
Remove unused same_dpcd variable.
Move PEAK_FACTOR_X1000 and LINK_TRAINING_MAX_VERIFY_RETRY
to the proper header for defining dc link internal constant.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Anson
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