Reviewed-by: Alex Hung
On 2024-07-22 05:28, Srinivasan Shanmugam wrote:
This commit addresses a potential null pointer dereference issue in the
`dcn401_init_hw` function. The issue could occur when `dc->clk_mgr` or
`dc->clk_mgr->funcs` is null.
The fix adds a check to ensure `dc->
Reviewed-by: Alex Hung
On 2024-07-22 04:51, Srinivasan Shanmugam wrote:
This commit addresses a potential null pointer dereference issue in the
`dcn30_init_hw` function. The issue could occur when `dc->clk_mgr` or
`dc->clk_mgr->funcs` is null.
The fix adds a check to ensure `dc->
Reviewed-by: Alex Hung
On 2024-07-22 05:14, Srinivasan Shanmugam wrote:
This commit addresses a potential null pointer dereference issue in the
`dcn32_init_hw` function. The issue could occur when `dc->clk_mgr` is
null.
The fix adds a check to ensure `dc->clk_mgr` is not null before
acc
Hi Melissa,
There are no commit messages in this patch.
Also, do you think this can be merged with Patch 5 "drm/amd/display:
remove redundant freesync parser for DP"?
On 2024-07-05 21:35, Melissa Wen wrote:
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
. It was only exercised with IGT tests.
v2: use const to fix warnings (Alex Hung)
v3: fix general protection fault on mst
v4: rename edid to drm_edid in amdgpu_connector (Jani)
call drm_edid_connector_update to clear edid in case of NULL (Jani)
keep setting NULL instead of free drm_edid
On 2024-07-05 21:35, Melissa Wen wrote:
Connectors have source physical address available in display
info. Use drm_dp_cec_attach() to use it instead of parsing the EDID
again.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++---
1 file changed, 2 ins
Can this be merged with [PATCH 10/11] drm/amd/display: get SADB from
drm_eld when parsing EDID caps
On 2024-07-05 21:35, Melissa Wen wrote:
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
On 2024-07-05 21:35, Melissa Wen wrote:
instead of parsing struct edid.
A more informative commit message will be helpful.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git
On 2024-07-05 21:35, Melissa Wen wrote:
instead of parsing struct edid.
A more informative commit message will be helpful.
Signed-off-by: Melissa Wen
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --gi
On 2024-07-28 19:32, Melissa Wen wrote:
On 07/25, Alex Hung wrote:
Hi Melissa,
There are no commit messages in this patch.
Also, do you think this can be merged with Patch 5 "drm/amd/display: remove
redundant freesync parser for DP"?
Hi Alex,
Thanks for your feedback.
I'
On 2024-07-28 20:02, Melissa Wen wrote:
On 07/25, Alex Hung wrote:
On 2024-07-05 21:35, Melissa Wen wrote:
instead of parsing struct edid.
A more informative commit message will be helpful.
sure. I'll improve it in the next version.
A soft reminder - a few other patches
This DC patchset brings improvements in multiple areas. In summary, we have:
* Fixes on DCN401, 3dlut and I2C
* Improvements on AC/DC, link rates, DSC and ODM slice rect and pipe
* Refactoring on code styles and unused code
Cc: Daniel Wheeler
Adam Nelson (1):
drm/amd/display: Fix 3dlut size f
From: Dillon Varone
Create dcn401 specific structure to encapsulate version specific
variables.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 +--
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 23
of DC mode limits
- set limits present if any clock has distinct AC and DC values from SMU
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Joshua Aberback
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 28 ++-
drivers/gpu/drm/amd/display/dc/dc.h
From: Rodrigo Siqueira
Cleanup unused code in DC.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 9 -
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 ---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 4
3
From: Rodrigo Siqueira
The CONNECTOR_ID_USBC check was removed to fix a regression, but it was
re-introduced by accident. This commit drops the USBC that causes the
regressions.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn32
From: Ilya Bakoulin
DP_DSC_CNTL no longer exists on DCN401.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Ilya Bakoulin
---
.../dc/dcn401/dcn401_dio_stream_encoder.c | 20 +++
1 file changed, 3 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu
From: Adam Nelson
[WHY]
After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is
incorrect.
[HOW]
Add register write to make valid.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Adam Nelson
---
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c| 8
From: Revalla Hari Krishna
[WHY]
Clean up the code that requires dccg to be in its own component.
[HOW]
Move all files under newly created dccg dir and fix the makefiles.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Revalla Hari Krishna
---
drivers/gpu/drm/amd/display
From: Samson Tam
Add VERTICAL_BLUR_SCALE & HORIZONTAL_BLUR_SCALE types.
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
From: Wenjing Liu
[WHY]
We need an unified location to perform ODM slice rect calculation.
[HOW]
Add three interfaces for ODM slice rect/width calucaltion in resource.h
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c
slightly different than
expected. This is usually imperceptible visually, but it impacts test
pattern CRCs for compliance test automation.
[HOW]
Update logic to use the register for adding extra left edge pixel for
YCbCr422/420 ODM cases.
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off-by
From: Sung Joon Kim
[WHY & HOW]
To support higher link rates that sink allows, we need to make
sure driver is ready and perform correct link-training sequence.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: Sung Joon Kim
---
.../gpu/drm/amd/display/dc/link/proto
From: Daniel Miess
[WHY & HOW]
Enable root clock optimization for SYMCLK and only
disable it when it's actively used.
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../amd/display/dc/d
From: George Shen
[WHY]
UHBR13.5 support is optional, even if UHBR20 is supported by the device.
If source supports max UHBR13.5 while sink, cable and LTTPR support
UHBR20 but not UHBR13.5, UHBR10 should be used as the max link cap.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by
From: Alvin Lee
[WHAT & HOW]
Fast updates can consist of some stream updates as well (i.e., out_csc).
In these cases we should not offload the flip to FW as we can only
offload address only updates to FW.
Reviewed-by: Chris Park
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers
DCN401 get_enc_caps function to allow the support for DSC slice count
higher than 4.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/dsc/dcn401/dcn401_dsc.c| 412 ++
1 file changed, 39 insertions(+), 373 deletions(-)
diff --git
HW, DCN IP,
SI and SW driver agrees that we can reduce I2C speed to 95kHz to address
the I2C spped fluctuation in DCN401.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Chris Park
---
.../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 4 ++--
1 file changed, 2
From: Dillon Varone
[WHY & HOW]
Refactor complex code into manageable functions. This also cleans up
some updating logics.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Dillon Varone
---
.../amd/display/dc/clk_mgr/dcn401/dalsmc.h| 8 +-
.../dc/clk_mgr/dc
the call to
get_max_flickerless_instant_vtotal_increase
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Ethan Bitnun
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +
.../gpu/drm/amd/display/dc/core/dc_stream.c | 64 +--
.../gpu/drm/amd/displa
From: Duncan Ma
[WHY]
DPIA boot option is set by VBIOS. It gets
overwritten when driver loads DMU.
[HOW]
Read PreOS boot options and determine if
dpia is enabled.
Reviewed-by: Ovidiu Bunea
Acked-by: Alex Hung
Signed-off-by: Duncan Ma
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
into component directory
- Fix 3dlut size for Fastloading on DCN401
- Fix write to non-existent reg on DCN401
- Remove USBC check for DCN32
- Remove unused code for some dc files
- Disable AC/DC codepath when unnecessary
- Create dcn401_clk_mgr struct
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
dr
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Add missing chips for HDCP
* Add new command to disable replay timing resync
* Fix encoder disable logic
* Enable DSC Flag in MST Mode Validation
* Change the DMCUB mailbox memory location from FB to inbox
* Add d
From: Aurabindo Pillai
[WHY & HOW]
Check whether get_subvp_en() callback exists before calling it.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Alex Hung
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgp
From: Yihan Zhu
[WHY & HOW]
MPC MCM low mem power optimization still causes color distortion on
first SCE enablement, only forces light sleep for it.
DPP low memory power optimization still needs this bit to save power.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-of
...@vger.kernel.org
Reviewed-by: Hansen Dsouza
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/dmub/src/dmub_srv.c| 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd
From: Fangzhi Zuo
[WHY & HOW]
For the scenario when a dsc capable MST sink device is directly
connected, it needs to use max dsc compression as the link bw constraint.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Roman Li
Acked-by: Alex Hung
Signed-of
: Martin Leung
Acked-by: Alex Hung
Signed-off-by: Mounika Adhuri
---
drivers/gpu/drm/amd/display/Makefile | 1 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/amd/display/dc/Makefile | 5 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 4 +-
.../gpu
From: Muhammad Ahmed
[WHY & HOW]
Add some null checks to fix an issue where 8k60
tiled display fails to light up.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Muhammad Ahmed
---
drivers/gpu/drm/amd/dis
...@vger.kernel.org
Reviewed-by: Aurabindo Pillai
Acked-by: Alex Hung
Signed-off-by: Tianci Yin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display
caps (HDR, OLED and etc)
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Anthony Koo
Acked-by: Alex Hung
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/dc_types.h| 1 +
drivers/gpu/drm/amd/display/dc/link/link_detection.c | 3 +++
2 files
From: Wenjing Liu
[WHY & HOW]
The current otg master pipe allocation logic is not optimized based
current resource context. We should try to acquire a free OTG master not
used in cur cts first to avoid unnecessary pipe switch from current
state.
Acked-by: Alex Hung
Signed-off-by: Wenjing
From: Daniel Miess
[WHY & HOW]
Enable DCN clock gating for DCN35.
Disable DTBCLK gate before link training
and re-enable afterwards
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Daniel Miess
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 6 ++-
.../gpu/drm
rent secondary pipes from ODM
or MPC combine.
Reviewed-by: Alvin Lee
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 37 ++-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 12 ++
2 files changed
poll for the bit to assert.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Duncan Ma
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 18 +-
drivers/gpu/drm/amd/display/dc/core/dc.c
Liu
Acked-by: Alex Hung
Signed-off-by: Duncan Ma
---
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 3 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 29 +++
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a
Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Lewis Huang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 22 -
.../gpu/drm/amd/display/dmub/src
can fit into end to end bw, mode supported
Reviewed-by: Wayne Lin
Acked-by: Alex Hung
Signed-off-by: Fangzhi Zuo
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 44 +++
1 file changed, 26 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgp
: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Nicholas Susanto
---
.../amd/display/dc/dcn35/dcn35_dio_stream_encoder.c| 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers
From: Krunoslav Kovac
[WHY & HOW]
PB9 bit 5 was added to signal PQ EOTF in AMD vendor specific infoframe.
This change sets it when appropriate.
Reviewed-by: Aric Cyr
Acked-by: Alex Hung
Signed-off-by: Krunoslav Kovac
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 6 -
From: Anthony Koo
[WHY & HOW]
Add new command to disable replay timing resync
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 41 +++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub
From: Rodrigo Siqueira
[WHAT]
Add missing HDCP ID in the message id enum.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/include/hdcp_msg_types.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/hdcp_msg_types.h
component directory
- Fix DSC not Enabled on Direct MST Sink
- Guard against invalid RPTR/WPTR being set
- Enable CM low mem power optimization
- Fix a debugfs null pointer error
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion
Thanks for catching this.
Reviewed-by: Alex Hung
On 2023-12-08 02:58, Harshit Mogalapalli wrote:
'wb_info' needs to be freed on error paths or it would leak the memory.
Smatch pointed this out.
Fixes: c81e13b929df ("drm/amd/display: Hande writeback request from userspace&
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes on DCN35 and DML2.
* Enhancements in DMUB.
* Improvements on IPS, DP and MPO and others.
Cc: Daniel Wheeler
Alvin Lee (2):
drm/amd/display: Add Replay IPS register for DMUB command table
drm/amd/displ
or active non-eDP screens.
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hw
d-by: Alex Hung
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 460a8010c79f..56feee0f
From: Alvin Lee
- Introduce a new Replay mode for DMUB version 0.0.199.0
Reviewed-by: Martin Leung
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc
From: Charlene Liu
[Why]
When mapping resources, resources could be unavailable.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Sung joon Kim
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
From: Nicholas Kazlauskas
[Why]
We can experience DENTIST hangs during optimize_bandwidth or TDRs if
FIFO is toggled and hangs.
[How]
Port the DCN35 fixes to DCN314.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off
.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 40 +--
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 5 +++
2 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc
Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 3 +++
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu
From: Ovidiu Bunea
[Why]
core_mode_programming in DML2 should output watermark calculations
to locals, but it incorrectly uses mode_lib
[How]
update code to match HW DML2
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed
r optimization again. All these pipe transitions happen
automatically and quietly when the conditions are met without any visual
impacts to the user.
Reviewed-by: Martin Leung
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c |
From: Charlene Liu
[Why]
Keep the same as previous APU and also insert clock dump
Reviewed-by: Ovidiu Bunea
Acked-by: Alex Hung
Signed-off-by: Charlene Liu
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 25 +--
.../dc/resource/dcn35/dcn35_resource.c| 2 +-
2
SKUs that have low memory bandwidth. In this case we need to
populate the optimal UCLK for each DCFCLK STA targets as the max
UCLK freq.
- Also fix a bug in DML where start_state is not assigned and used
correctly.
Reviewed-by: Samson Tam
Reviewed-by: Chaitanya Dhere
Acked-by: Alex Hung
and guarantees
the head pipe will have matching otg inst and pipe idx.
Reviewed-by: Gabe Teeger
Acked-by: Alex Hung
Signed-off-by: Dmytro Laktyushkin
---
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 36 ++-
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm
scenarios.
[How]
Add DP audio bandwidth validation for 8b/10b MST and 128b/132b SST/MST
cases and filter out modes that cannot be supported with the current
timing config.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/dce/dce_audio.c
() and amdgpu_dm_set_replay_caps()
to fix the issue in the earlier commit that cause PSR and Replay
enabled at the same time.
Reviewed-by: Sun peng Li
Acked-by: Alex Hung
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++-
.../amd/display/amdgpu_dm
ns false always get called when IPS
is supported.
Further rework/redesign is needed to decide whether we need a separate
level of DM allow vs DC allow and when to attempt re-entry.
Reviewed-by: Yihan Zhu
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers
From: Nicholas Kazlauskas
[Why & How]
Match DCN314's policy.
Reviewed-by: Gabe Teeger
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
1 file changed, 1 insertion(+)
dif
nt on the active stream case.
Z8 will still be blocked based on stutter duration, which is likely to
be the case for most multi plane configurations.
Reviewed-by: Gabe Teeger
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dml/
reported by legacy DP as EIO.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm
resource checks
- Add Replay IPS register for DMUB command table
- Init link enc resources in dc_state only if res_pool presents
- Allow IPS2 during Replay
Acked-by: Alex Hung
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Thanks for catching this.
Reviewed-by: Alex Hung
On 2024-01-13 02:11, Srinivasan Shanmugam wrote:
Return value of 'to_amdgpu_crtc' which is container_of(...) can't be
null, so it's null check 'acrtc' is dropped.
Fixing the below:
drivers/gpu/drm/amd/amdgpu/..
On 2024-01-26 09:28, Melissa Wen wrote:
Replace raw edid handling (struct edid) with the opaque EDID type
(struct drm_edid) on amdgpu_dm_connector for consistency. It may also
prevent mismatch of approaches in different parts of the driver code.
Working in progress. There are a couple of cast
On 2023-08-29 11:03, Jani Nikula wrote:
On Tue, 29 Aug 2023, Jani Nikula wrote:
On Tue, 29 Aug 2023, Alex Deucher wrote:
On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
On Wed, 23 Aug 2023, Jani Nikula wrote:
On Tue, 22 Aug 2023, Alex Hung wrote:
On 2023-08-22 06:01, Jani Nikula
On 2023-08-30 01:29, Jani Nikula wrote:
On Tue, 29 Aug 2023, Alex Hung wrote:
On 2023-08-29 11:03, Jani Nikula wrote:
On Tue, 29 Aug 2023, Jani Nikula wrote:
On Tue, 29 Aug 2023, Alex Deucher wrote:
On Tue, Aug 29, 2023 at 6:48 AM Jani Nikula wrote:
On Wed, 23 Aug 2023, Jani Nikula
[WHY]
edid_override and drm_edid_override_connector_update, according to drm
documentation, should not be referred outside drm_edid.
[HOW]
Remove and replace them accordingly.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++-
1 file changed, 2
Reviewed-by: Alex Hung
On 2023-08-16 15:26, Alex Hung wrote:
From: Harry Wentland
[WHY]
Previously this only excluded build for a few amdgpu_dm
binaries which makes no sense.
[HOW]
Wrap the entire Makefile in "ifneq ($(CONFIG_DRM_AMD_DC),)"
Signed-off-by: Harry Wentland
Sig
Reviewed-by: Alex Hung
On 2023-08-16 15:26, Alex Hung wrote:
From: Harry Wentland
[WHAT]
Prepare a virtual connector for writeback.
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +--
drivers/gpu/drm/amd
Reviewed-by: Alex Hung
On 2023-08-16 15:26, Alex Hung wrote:
From: Harry Wentland
[WHY]
Writeback connectors are based on a different object:
drm_writeback_connector, and are therefore different from
amdgpu_dm_connector. We need to be careful to ensure code
designed for amdgpu_dm_connector
Reviewed-by: Alex Hung
On 2023-08-16 15:26, Alex Hung wrote:
From: Harry Wentland
[WHY]
We will be dealing with two types of connector: amdgpu_dm_connector
and drm_writeback_connector.
[HOW]
We want to find both and then cast to the appriopriate type afterwards.
Signed-off-by: Harry
Reviewed-by: Alex Hung
On 2023-08-16 15:26, Alex Hung wrote:
From: Harry Wentland
[WHAT]
We need to use this function for both amdgpu_dm_connectors
and drm_writeback_connectors. Modify it to operate on
a drm_connector as a common base.
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
Reviewed-by: Alex Hung
On 2023-08-16 15:26, Alex Hung wrote:
From: Harry Wentland
[WHAT]
Again, we need to use this function for writeback connectors,
which are not of type amdgpu_dm_connector. Use the common base
drm_connector instead.
Signed-off-by: Harry Wentland
Signed-off-by: Alex
Reviewed-by: Alex Hung
On 2023-08-16 15:26, Alex Hung wrote:
From: Harry Wentland
[WHY]
We need to track the dc_link and it would get confusing if
re-using the amdgpu_dm_connector.
[HOW]
Creating new amdgpu_dm_wb_connector.
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
Reviewed-by: Alex Hung
On 2023-08-16 15:26, Alex Hung wrote:
From: Harry Wentland
[WHAT]
Writeback connectors don't have a physical sink but DC still
needs a sink to function. Create a fake sink and stream for
writeback connectors
Signed-off-by: Harry Wentland
Signed-off-by: Alex
ies is
Reviewed-by: Harry Wentland
Harry
On 2023-08-16 17:26, Alex Hung wrote:
This patchset adds drm_writeback connector supports and enables display
writeback block (DWB) in AMD hardware.
The function can be tested by IGT's kms_writeback test which also
requires a number of pat
[WHY]
edid_override and drm_edid_override_connector_update, according to drm
documentation, should not be referred outside drm_edid.
[HOW]
Remove and replace them accordingly. This can tested by IGT's
kms_hdmi_inject test.
Signed-off-by: Alex Hung
---
V2 - add comments for drm_get_edi
On 2023-09-18 04:25, Jani Nikula wrote:
On Fri, 15 Sep 2023, Alex Hung wrote:
[WHY]
edid_override and drm_edid_override_connector_update, according to drm
documentation, should not be referred outside drm_edid.
[HOW]
Remove and replace them accordingly. This can tested by IGT&#
[WHY]
edid_override and drm_edid_override_connector_update, according to drm
documentation, should not be referred outside drm_edid.
[HOW]
Remove and replace them accordingly. This can tested by IGT's
kms_hdmi_inject test.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdg
On 2022-09-14 07:40, Michel Dänzer wrote:
On 2022-09-14 15:31, Michel Dänzer wrote:
On 2022-09-14 07:10, Wayne Lin wrote:
From: Alex Hung
[Why & How]
This fixes kernel errors when IGT disables primary planes during the
tests kms_universal_plane::functional_test_pipe/pageflip_test_
On 2022-09-14 10:55, Michel Dänzer wrote:
[ Adding the dri-devel list ]
On 2022-09-14 18:30, Alex Hung wrote:
On 2022-09-14 07:40, Michel Dänzer wrote:
On 2022-09-14 15:31, Michel Dänzer wrote:
On 2022-09-14 07:10, Wayne Lin wrote:
From: Alex Hung
[Why & How]
This fixes kernel er
_3d_mode_17_12bit;
};
struct drm_color_pipeline_lut3d_data {
*lut_3d;
};
and etc.
3. A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Related Work:
- Enable 3D LUT to AMD display drivers
(https://www.spinics.net/lists/amd-gfx/msg83032.html)
A struct is defined for 3D LUT modes to be supported by hardware.
The elements includes lut_isze, lut_stride, bit_depth, color_format
and flags.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
--
t.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++
drivers/gpu/drm/drm_atomic_state_helper.c | 3 ++
drivers/gpu/drm/drm_atomic_uapi.c | 11 ++
drivers/gpu/drm/drm_color_mgmt.c | 37 +++
include/drm/drm_mod
Add a 3D LUT mode supported by amdgpu driver.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/modules/color/color_gamma.h | 12
1 file changed, 12
Enable the 3D LUT mode supported by amdgpu.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++
drivers/gpu/drm/drm_color_mgmt.c
Implement the 3D LUT interface, convert and pass the data for amdgpu
driver.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++
.../g
tures")
Signed-off-by: Alex Hung
---
drivers/acpi/x86/s2idle.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c
index bfe611dc08cc..3d0cf0ace4a9 100644
--- a/drivers/acpi/x86/s2idle.c
+++ b/drivers/acpi/x86/s2idle.c
@@ -475,7 +475,6 @@
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