Hi all,
Friendly ping: who can take this, please? :)
Thanks!
--
Gustavo
On 14/02/25 18:48, Gustavo A. R. Silva wrote:
-Wflex-array-member-not-at-end was introduced in GCC-14, and we are
getting ready to enable it, globally.
So, in order to avoid ending up with a flexible-array member in the
m
[Public]
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Friday, March 7, 2025 2:46 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 02/11] drm/amdgpu: add ring flag for no user submissions
>
> This would be set by IPs which only accept submissions from the k
From: "jesse.zh...@amd.com"
This patch introduces two new functions, `amdgpu_sdma_stop_queue` and
`amdgpu_sdma_start_queue`, to handle the stopping and starting of SDMA queues
during engine reset operations. The changes include:
1. **New Functions**:
- `amdgpu_sdma_stop_queue`: Stops the SDMA
Em 01/03/2025 03:04, Raag Jadav escreveu:
On Fri, Feb 28, 2025 at 06:49:43PM -0300, André Almeida wrote:
Hi Raag,
On 2/28/25 11:58, Raag Jadav wrote:
On Fri, Feb 28, 2025 at 09:13:53AM -0300, André Almeida wrote:
To notify userspace about which app (if any) made the device get in a
wedge stat
On 2025-03-09 23:01, Yifan Zha wrote:
> [Why]
> If reset is detected and kfd need to evict working queues, HWS moving queue
> will be failed.
> Then remaining queues are not evicted and in active state.
>
> After reset done, kfd uses HWS to termination remaining activated queues but
> HWS is re
Only increment the power profile on the first submission.
Since the decrement may end up being pushed out as new
submissions come in, we only need to increment it once.
Fixes: 1443dd3c67f6 ("drm/amd/pm: fix and simplify workload handling”)
Cc: Yang Wang
Cc: Kenneth Feng
Signed-off-by: Alex Deuch
Only increment the power profile on the first submission.
Since the decrement may end up being pushed out as new
submissions come in, we only need to increment it once.
Fixes: 1443dd3c67f6 ("drm/amd/pm: fix and simplify workload handling”)
Cc: Yang Wang
Cc: Kenneth Feng
Signed-off-by: Alex Deuch
[AMD Official Use Only - AMD Internal Distribution Only]
Please add following information into commit message.
Fixes: bd3c9d1cde0c ("drm/amd/pm: fix and simplify workload handling”）
Series is
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: Kenneth Feng
Sent: Tues
On Mon, Mar 10, 2025 at 8:53 PM Shaoyun Liu wrote:
>
> When MES is been used , the set_hw_resource_1 API is required to
> initialize MES internal context correctly
>
> Signed-off-by: Shaoyun Liu
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 6 +--
> drivers/gpu/dr
Em 01/03/2025 02:53, Raag Jadav escreveu:
On Fri, Feb 28, 2025 at 06:54:12PM -0300, André Almeida wrote:
Hi Raag,
On 2/28/25 11:20, Raag Jadav wrote:
Cc: Lucas
On Fri, Feb 28, 2025 at 09:13:52AM -0300, André Almeida wrote:
When a device get wedged, it might be caused by a guilty application.
Hello Nicholas Kazlauskas,
Commit 88694af9e4d1 ("drm/amd/display: Expose HDR output metadata for
supported connectors") from May 28, 2019 (linux-next), leads to the
following Smatch static checker warning:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:10751
dm_update_crtc_s
From: "jesse.zh...@amd.com"
This patch introduces two new callbacks, `stop_queue` and `start_queue`, to the
`amdgpu_ring_funcs` structure. These callbacks are designed to handle the
stopping
and starting of SDMA queues during engine reset operations. The changes include:
1. **Addition of Callba
On the off chance that command stream passed from userspace via
ioctl() call to radeon_vce_cs_parse() is weirdly crafted and
first command to execute is to encode (case 0x0301), the function
in question will attempt to call radeon_vce_cs_reloc() with size
argument that has not been properly ini
This is a bug fix. The scenario is that the same client can add the certain
workload type refcount multiple times. Then the same client can not remove
this setting when it wants to get back to the default bootup workload.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
[AMD Official Use Only - AMD Internal Distribution Only]
Please correct the code comments before committing the patch.
/* 1 second timeout */ 10ms
With that fixed,
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: Kenneth Feng
Sent: Tuesday, March 11, 2025 16:55
Am 11.03.25 um 09:32 schrieb jesse.zh...@amd.com:
> From: "jesse.zh...@amd.com"
>
> This patch introduces two new callbacks, `stop_queue` and `start_queue`, to
> the
> `amdgpu_ring_funcs` structure. These callbacks are designed to handle the
> stopping
> and starting of SDMA queues during engine
Am 11.03.25 um 09:33 schrieb jesse.zh...@amd.com:
> From: "jesse.zh...@amd.com"
>
> This patch introduces two new functions, `amdgpu_sdma_stop_queue` and
> `amdgpu_sdma_start_queue`, to handle the stopping and starting of SDMA queues
> during engine reset operations. The changes include:
>
> 1. **
This macro guard "__cplusplus" is unnecessary and should not be there.
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h
b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h
inde
Applied. thanks!
On Mon, Mar 10, 2025 at 6:48 AM Dan Carpenter wrote:
>
> These lines are indented one tab more than they should be. Delete
> the stray tabs.
>
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 12 ++--
> 1 file changed, 6 insertions(+), 6
Add error handling to propagate amdgpu_cgs_create_device() failures
to the caller. When amdgpu_cgs_create_device() fails, release hwmgr
and return -ENOMEM to prevent null pointer dereference.
[v1]->[v2]: Change error code from -EINVAL to -ENOMEM. Free hwmgr.
Signed-off-by: Wentao Liang
---
driv
Reviewed-by: Amber Lin
Regards,
Amber
On 3/6/25 14:52, Harish Kasiviswanathan wrote:
0x9
Reviewed-by: Sunil Khatri
On 3/7/2025 8:45 PM, Alex Deucher wrote:
Move it to amdgpu_mes to align with the compute and
sdma hqd masks. No functional change.
v2: rebase on new changes
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 22 ++
driver
Reviewed-by: Sunil Khatri
On 3/6/2025 2:17 AM, Alex Deucher wrote:
Plumb in support for disabling kernel queues in
GFX11. We have to bring up a GFX queue briefly in
order to initialize the clear state. After that
we can disable it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgp
For coherence with DCE8 et DCE10, add or move some values under sid.h
and remove duplicated from si_enums.h.
Signed-off-by: Alexandre Demers
---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 63 ++-
drivers/gpu/drm/amd/amdgpu/si_enums.h | 6 ---
drivers/gpu/drm/amd/amdgpu/sid.
Reviewed-by: Sunil Khatri
On 3/6/2025 2:17 AM, Alex Deucher wrote:
On chips that support user queues, setting this option
will disable kernel queues to be used to validate
user queues without kernel queues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
driv
On 2025-02-25 06:18, Louis Chauvet wrote:
> Le 20/12/2024 à 05:33, Alex Hung a écrit :
>> From: Harry Wentland
>>
(snip)
>> + { 0xfbfb, 0xfbfb, 0xfbfb, 0 },
>> + { 0xfcfc, 0xfcfc, 0xfcfc, 0 },
>> + { 0xfdfd, 0xfdfd, 0xfdfd, 0 },
>> + { 0xfefe, 0xfefe, 0xfefe, 0 },
>> + { 0x
Add callbacks for fan speed fetching.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4034
Signed-off-by: Alex Deucher
---
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2
Applied. Thanks!
Alex
On Tue, Mar 11, 2025 at 7:23 AM Nikita Zhandarovich
wrote:
>
> On the off chance that command stream passed from userspace via
> ioctl() call to radeon_vce_cs_parse() is weirdly crafted and
> first command to execute is to encode (case 0x0301), the function
> in questi
[Public]
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Friday, March 7, 2025 11:16 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 03/11] drm/amdgpu/gfx: add generic handling for disable_kq
>
> Add proper checks for disable_kq functionality in gfx helper f
Only increment the power profile on the first submission.
Since the decrement may end up being pushed out as new
submissions come in, we only need to increment it once.
Fixes: 1443dd3c67f6 ("drm/amd/pm: fix and simplify workload handling”)
Cc: Yang Wang
Cc: Kenneth Feng
Signed-off-by: Alex Deuch
On 2025-02-25 06:19, Louis Chauvet wrote:
>
>
> Le 20/12/2024 à 05:33, Alex Hung a écrit :
>> From: Harry Wentland
>>
>> Two tests are added to VKMS LUT handling:
>> - linear
>> - inv_srgb
>>
>> Reviewed-by: Louis Chauvet
>> Signed-off-by: Alex Hung
>> Signed-off-by: Harry Wentland
>> ---
> > register_chrdev() registers 256 minor numbers, calling it will result in
> > calling kmalloc_array(256, sizeof(struct probe), GFP_KERNEL) whereas
> > calling alloc_chrdev_region() with count parameter equals to 1, which is
> > the number of minor numbers requested, will result in calling
> > km
On 07.03.25 09:39, Christian König wrote:
Am 06.03.25 um 18:01 schrieb Natalie Vock:
When userspace requests buffers to be placed into GTT | VRAM, it is
requesting the buffer to be placed into either of these domains. If the
buffer fits into VRAM but does not fit into GTT, then let the buffer
re
Reviewed-by: Sunil Khatri
On 3/7/2025 8:45 PM, Alex Deucher wrote:
This would be set by IPs which only accept submissions
from the kernel, not userspace, such as when kernel
queues are disabled. Don't expose the rings to userspace
and reject any submissions in the CS IOCTL.
Signed-off-by: Alex
Am 07.03.25 um 20:10 schrieb Salah Triki:
> On Wed, Mar 05, 2025 at 07:18:33PM -0500, Felix Kuehling wrote:
>> On 2025-03-05 16:08, Salah Triki wrote:
>>> Replace (un)register_chrdev() by (unregister/alloc)_chrdev_region() as
>>> they are deprecated since kernel 2.6.
>> Where is that information co
On 03/11, Alex Hung wrote:
> This macro guard "__cplusplus" is unnecessary and should not be there.
>
> Signed-off-by: Alex Hung
> ---
> drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h
> b/driv
On Wed, Mar 5, 2025 at 8:57 PM Alexandre Demers
wrote:
>
> Let's finish the cleanup in sid.h to calm down things after wiring it into
> dce_v6_0.c.
>
> This is a bigger cleanup.
> Many defines found under sid.h have already been properly moved
> into the different "_d.h" and "_sh_mask.h", so they
Applied the series. Thanks!
Alex
On Sun, Mar 9, 2025 at 12:49 PM Alexandre Demers
wrote:
>
> For coherence with DCE8 et DCE10, add or move some values under sid.h
> and remove duplicated from si_enums.h.
>
> Signed-off-by: Alexandre Demers
> ---
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 63 ++
When the parameter is set, disable user submissions
to kernel queues.
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/sdm
When MES is been used , the set_hw_resource_1 API is required to
initialize MES internal context correctly
Signed-off-by: Shaoyun Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 6 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 +--
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 52 ++
[Public]
Reviewed-by: Mukul Joshi
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, March 11, 2025 4:06 PM
> To: Deucher, Alexander
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu/mes: remove unused functions
>
> Ping?
>
> On Wed, M
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Harish
Kasiviswanathan
Sent: Wednesday, March 12, 2025 02:17
To: amd-gfx@lists.freedesktop.org
Cc: Kasiviswanathan, Harish
Subject: [PATCH
From: Cruise Hung
[WHY & HOW]
The response of DP BW allocation is handled in Outbox ISR.
When it failed to request the DP BW allocation, it sent another
DPCD request in Outbox ISR immediately. The DP AUX reply also
uses the Outbox ISR. So, no AUX reply happened in this case.
Change to use HPD IRQ
From: Yilin Chen
[WHY]
The info message was wrong when support_edp0_on_dp1 is enabled
[HOW]
Use correct info message for support_edp0_on_dp1
Fixes: c1037b2ed7ba ("drm/amd/display: add a quirk to enable eDP0 on DP1")
Reviewed-by: Aurabindo Pillai
Signed-off-by: Yilin Chen
Signed-off-by: Alex H
From: Taimur Hassan
This version brings along following fixes:
- Use DPM table clk setting for dml2 soc dscclk
- Update static soc table
- Fix incorrect fw_state address in dmub_srv
- Use HW lock mgr for PSR1 when only one eDP
- Revert "Support for reg inbox0 for host->DMUB CMDs"
- Change notific
From: Dillon Varone
This reverts commit b4a8503f69c214987b30cb7d8c3399d50477adac.
Reason: Cursor movement causes system to hang.
Reviewed-by: Aric Cyr
Signed-off-by: Dillon Varone
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 185 +--
drivers/gpu/drm/a
From: Jing Zhou
[WHY]
We should never apply a minimum dispclk value while in
prepare_bandwidth or while displays are active. This is
always an optimizaiton for when all displays are disabled.
[HOW]
Defer dispclk optimization until safe_to_lower = true
and display_count reaches 0.
Since 0 has a
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes on DCN31 and DML2;
* Enhancements in DMUB;
* Improvements on DP, eDP and others.
Cc: Daniel Wheeler
Alex Hung (1):
drm/amd/display: Check pipe->stream before passing it to a function
Charlene Liu (2):
From: Ryan Seto
[WHY & HOW]
Fixed Overflow issue by clamping VStartup to max value of register.
Reviewed-by: Alvin Lee
Signed-off-by: Ryan Seto
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/g
From: Mario Limonciello
[WHY]
DMUB locking is important to make sure that registers aren't accessed
while in PSR. Previously it was enabled but caused a deadlock in
situations with multiple eDP panels.
[HOW]
Detect if multiple eDP panels are in use to decide whether to use
lock. Refactor the fu
From: Lo-an Chen
[WHY]
The fw_state in dmub_srv was assigned with wrong address.
The address was pointed to the firmware region.
[HOW]
Fix the firmware state by using DMUB_DEBUG_FW_STATE_OFFSET
in dmub_cmd.h.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Lo-an Chen
Signed-off-by: Alex Hung
On 07/02/2025 23:38, Jay Cornwall wrote:
VALU instructions with SGPR source need wait states to avoid hazard
with SALU using different SGPR.
v2: Eliminate some hazards to reduce code explosion
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
Hi,
That looks good to me, thanks. Sorry for the
[WHAT & HOW]
dp_is_128b_132b_signal dereferences pipe->stream so it is necessary to
check it in advance.
Also fix erroneous spaces and move a variable declaration to top.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Alex Hung
---
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 15 ++---
From: Charlene Liu
[WHY]
Not like dppclk/dispclk, dml2 will calculate the minimum required clocks.
For dscclk, it is used for pure comparision.
Reviewed-by: Alvin Lee
Signed-off-by: Charlene Liu
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 2 +-
These lines are indented one tab more than they should be. Delete
the stray tabs.
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
b/drivers/gpu/drm/am
Wire up the query.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index e4089fd58711c
Make it visible for the all GC 11.x chips that support it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e46
Wire up the query.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 10 ++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 10 ++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
b/d
Make it visible for the all GC 12.x chips that support it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index bb39e7f83341b..c5abf
Make it visible for the all GC 9.3.0 chips that support it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index c5abf4eacbfcd..3ff97
Wire up the query.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 37d82a71a2d7c..9481f897432d7 10064
Ping?
On Wed, Mar 5, 2025 at 4:08 PM Alex Deucher wrote:
>
> Leftover from the MES self tests that were removed previously.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 800
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 41 --
> 2 fil
remove unnecessary ra ta laods if the module parameter is specified.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
ind
Added checks for NULL values after retrieving drm_new_conn_state and
drm_old_conn_state to prevent dereferencing NULL pointers.
Fixes the below:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:10751
dm_update_crtc_state()
warn: 'drm_new_conn_state' can also be NULL
drivers/gp
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Alex,
I tested this patch. After the desktop is launched, at a certain time, the
workload is set to 3d fullscreen twice, then
The idle worker can't set it back to bootup default.
Is it expected?
Thanks.
-Original Message-
From:
[AMD Official Use Only - AMD Internal Distribution Only]
Series is Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, March 12, 2025 4:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/6] drm/amdgpu/pm:
Ping on this series?
Thanks,
Alex
On Wed, Mar 5, 2025 at 4:07 PM Alex Deucher wrote:
>
> Just use the default values. There's not need to
> get the value from hardware and it could cause problems
> if we do that at runtime and gfxoff is active.
>
> Signed-off-by: Alex Deucher
> ---
> drivers
[Public]
Series is:
Reviewed-by: Mukul Joshi
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, March 11, 2025 4:06 PM
> To: Deucher, Alexander
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/amdgpu/gfx12: don't read registers in mqd in
Thanks for catch up and fix this race condition. It looks good to me.
One minor thing below:
On 3/6/2025 12:03 AM, Emily Deng wrote:
Issue:
In the scenario where svm_range_restore_pages is called, but svm->checkpoint_ts
has not been set and the retry fault has not been drained,
svm_range_unm
Applied. Thanks!
On Thu, Mar 6, 2025 at 9:13 AM Aliaksei Urbanski
wrote:
>
> Starting from 6.11, AMDGPU driver, while being loaded with amdgpu.dc=1,
> due to lack of .is_two_pixels_per_container function in dce60_tg_funcs,
> causes a NULL pointer dereference on PCs with old GPUs, such as R9 280X
[AMD Official Use Only - AMD Internal Distribution Only]
Let's not do that. Ras ta should still be functioning to forward disable
feature command even software ras is disabled by ras_enable.
Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin)
Sent: Wednesday, March 12, 2025 09:
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Kenneth Feng kenneth.f...@amd.com
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, March 11, 2025 10:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu
On 3/12/2025 11:16 AM, Asad Kamal wrote:
> Update feature list for smu_v13_0_12 to show vcn & smu deep
> sleep feature enable status.
>
> Signed-off-by: Asad Kamal
> Reviewed-by: Hawking Zhang
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
for old asics that do not support mca translating, we
just save PA for them
Signed-off-by: ganglxie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 24 ---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 9 +--
2 files changed, 28 insertions(+), 5 deletions(-)
diff --gi
On 3/12/2025 2:14 AM, Alex Deucher wrote:
> Wire up the query.
>
> Signed-off-by: Alex Deucher
Series is -
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/
[AMD Official Use Only - AMD Internal Distribution Only]
It is ok, thank you for your explanation.
Best Regards,
Kevin
-Original Message-
From: Zhang, Hawking
Sent: Wednesday, March 12, 2025 11:58
To: Wang, Yang(Kevin) ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao
Subject: RE: [PATCH]
Modern APU and dGPU require DC support to be able to light up the
display. If DC support has been disabled either by kernel config
or by kernel command line the screen will visibly freeze when the
driver finishes early init.
As it's known before early init is done whether DC support is required
d
From: Charlene Liu
[WHY]
Update the static soc table dcn3_5_soc.
Reviewed-by: Alvin Lee
Signed-off-by: Charlene Liu
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/displa
On Tue, Mar 11, 2025 at 5:03 AM Kenneth Feng wrote:
>
> This is a bug fix. The scenario is that the same client can add the certain
> workload type refcount multiple times. Then the same client can not remove
> this setting when it wants to get back to the default bootup workload.
This will break
On 3/12/2025 2:14 AM, Alex Deucher wrote:
> Wire up the query.
>
> Signed-off-by: Alex Deucher
Series is -
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/
Update feature list for smu_v13_0_12 to show vcn & smu deep
sleep feature enable status.
Signed-off-by: Asad Kamal
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 5 +
2 files changed, 8 i
Encode socket id to CPER record id to be unique across devices.
v2: add pointer check for adev->smuio.funcs->get_socket_id
v2: set 0 if adev->smuio.funcs->get_socket_id is NULL
Signed-off-by: Xiang Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c | 18 +-
1 file changed, 13 inse
Expose unique_id for gfx12
Signed-off-by: Harish Kasiviswanathan
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 1d04f1b79ded..2179344e78d9 100644
--- a/drivers/gpu/drm/amd
Add description for debug_mask bit options.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 22775c204632..04b518417da0 100644
--
Reviewed-by: Alex Deucher
On Tue, Mar 11, 2025 at 2:17 PM Harish Kasiviswanathan
wrote:
>
> Expose unique_id for gfx12
>
> Signed-off-by: Harish Kasiviswanathan
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_p
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